"float PHYs", communication between indirect attached devices

[Stefan Bethke]

Am 10.12.2011 um 13:05 schrieb Aleksandr Rybalko:

> Hi net@ subscribers,
> 
> Simple explanation of problem: 
> real situation, device with two NICs (arge0 and arge1)
> arge0 attached to PHY w/o direct access to it.
> arge1 attached to switch MII port (and have access to MDIO bus).
> 
> switch have child MDIO bus for all Physical ports.
> One of this ports (or his PHY) must be controlled by arge0.
> 
> I will do pseudo PHY driver that must communicate with real one on
> switch MDIO bus.
> 
> Question: how to communicate, since newbus can't handle two parents:
> 1) sysctl
> 2) events
> 3) kenv
> 4) something better
> globals is not a solution, because it is possible that we will have
> some device with more than one "float PHYs"
> 
> please, help me to find best way!
> 
> Wait for your suggestions, comments, hints, etc.

I'll trx to explain with a bit more detail what the situation is, and what variations we're encountering with the various embedded systems that have a switch connected to one or more ethernet ports of the SoC.

Right now Adrian, Aleksadr and I are trying to add configuration support for the switch controllers in small WLAN routers based on the various Atheros SoC and a variety of switch controllers.  As different as they might be, they are usually attached in one of these ways:

- the ethernet interface is connected via MII, RGMII or GMII to one of the MACs on the switch (back to back, no PHY).  The switch might have PHYs attached to its other ports, but as far as the SoC ethernet interfaces are concerned, there's nothing to be configured.

- the interface is connected to a PHY via MII, but the PHYs MDIO slave is not connected to the ethernet interface's MDIO master.

Both can exist at the same time; e.g in many wlan routers, arge0 is connected to a PHY in the switch chip, while arge1 is connected to one of the switch port MACs.

The switch controller can be connected to the SoC via I2C (e.g. RTL83XX series), or through an MDIO interface (AR8x16, RTL830x).

The switch controller has its own MDIO master, controlled through the switch register set, to communicate with the built-in PHYs.

To further confuse things: the PHY that arge0 is connected to can only be controlled by talking to the switch that is connected to arge1's MDIO master, in turn talking to the switch's MDIO master to talk to the PHY.

This poses a number of challenges:

- ethernet switches that are attached via MDIO may not look like PHYs, in particular, they might not have a BMSR or ID1 and ID2.  This is the case with the Atheros AR8x16 series.  The miibus code assumes that all possible children of an miibus are PHYs, and will not easily accept non-PHY children.

- attach hierarchy and sequence, e.g. for the PHY in the switch chip, where the switch chip is attached to arge1, but the PHY needs to be at arge0.

- creating miibus'ses that are not associated with an interface.  The miibus code assumes that any PHY is attached to an MII connected to an ethernet interfaces MAC.  The switch ports are not part of the ethernet interfaces, and their MAC configuration doesn't change when one of the switch ports negotiate a different media setting.


Stefan

-- 
Stefan Bethke <stb at lassitu.de>   Fon +49 151 14070811