igb interrupt moderation

[Michael Tüxen]

Dear all,

I just figured out that there is a newer version of the spec
available: 2.45. Some of the issues as indicated inline
are already resolved. 

Best regards
Michael

On Jan 3, 2010, at 2:55 PM, Michael Tüxen wrote:

> Hi Barney, Hi Jack,
> 
> some comments and some more questions inside...
> 
> Best regards
> Michael
> 
> On Jan 2, 2010, at 8:42 PM, Barney Cordoba wrote:
> 
>> Jack,
>> 
>> I'm trying to get some clarification on differences I'm finding between
>> the 82575 and 82576 parts with respect to interrupt moderation. The spec
>> I have for the 82576 (82576_Datasheet_v2p1.pdf) indicates that the 
> I'm only commenting 82576. You can get rev 2.41 from intels website...
It is really 2.45 now
>> 
>> ITR algorithm is different than the one used (I don't have one of the
>> secret copies of the 82575 spec). The algorithm shown is
>> 
>> interrupts/sec = 1/(2 * 10-6sec x interval) (page 295, Section 7.3.4)
>> 
>> which is clearly wrong from practice. I have an 82576 (device id 10C9)
> If you look at section 8.8.12, you find other formulas...
> Jack: Which ones are correct?
The formulas is 8.8.12 are gone. Issue resolved.
>> if I use the 125d setting in the example get just under 32000 interrupts
>> per second. Clearly your code doesnt implement this, nor do you have
>> different settings for the 82575 and 82576 parts. So I assume that the 
>> same formula for the em parts hold for the igb parts, and that the 
>> datasheet is wrong?
>> 
>> There does seem to be a slight difference. The setting that gets 1000
>> ints/second on the 82575 generates about 1020 on the 82576. Not a big
>> deal but I wonder why there's a difference? Is the reference clock for
>> these something that may not be fixed and could vary from board to 
>> board? Note that both devices are on the same MB.
>> 
>> Also, it seems that settings to EITR over 32767 wrap on the 82576 (for
>> example writing 32768 to EITR is the same as writing a 1). So the  minimum setting on the 82576 is around 125 ints/second. The 82575 can accept 
>> values up the 65535 before wrapping. 
> Hmm, looking at the table in 8.8.12 would suggest:
> Setting it to one sets a reserved bit, but does not change the interval.
> Setting it to 2^15 should set the LLI_EN bit, but does not change in interval.
> 
> Jack is setting the register to
> igb_low_latency: 128
> igb_ave_latency: 450
> igb_bulk_latency: 1200
> 
> This would result in intervals of:
> igb_low_latency: 32
> igb_ave_latency: 112
> igb_bulk_latency: 300
> Jack: What are the corresponding interrupt rates? The spec provides different
>      formulas and talks about a 1us, 2us or 8us counter. Not sure what is right...
The interrupt rates are according to the formula in the spec
igb_low_latency: 31250
igb_ave_latency: 8929
igb_bulk_latency: 3333
Jack: Is this right?
> Jack: Why are you setting bit1 (which is reserved) in the case igb_ave_latency?
Still valid.
> 
> And another question for Jack:
> In igb_update_aim() you do
> 	if (olditr != newitr) {
> 		/* Change interrupt rate */
> 		rxr->eitr_setting = newitr;
> 		E1000_WRITE_REG(&adapter->hw, E1000_EITR(rxr->me),
> 		    newitr | (newitr << 16));
> 	}
> So why are setting the higher bits of the EITR? You are setting
> igb_low_latency: the LL Counter becomes 0, the moderation counter becomes 16
> igb_ave_latency: the LL Counter becomes 2, the moderation counter becomes 56
> igb_bulk_latency: the LL Counter becomes 16, the moderation counter becomes 148
Still valid.
> 
> I really do not understand these settings. Maybe the spec is wrong? Or you do mean
> 	if (olditr != newitr) {
> 		/* Change interrupt rate */
> 		rxr->eitr_setting = newitr;
> 		E1000_WRITE_REG(&adapter->hw, E1000_EITR(rxr->me), newitr);
> 	}
> Or do you want to preserve the counters, set the CNT_INGR bit and mean
> 	if (olditr != newitr) {
> 		/* Change interrupt rate */
> 		rxr->eitr_setting = newitr;
> 		E1000_WRITE_REG(&adapter->hw, E1000_EITR(rxr->me), 0x80000000 | newitr);
> 	}
> 
> Could you clarify that?
Still valid.
>> 
>> The 82576 document doesn't have a map of the register that I can find, so
>> Im curious as to whether these observations are something I can assume is
>> true across all parts and motherboards/cards, or is there some
>> implementation variance that will cause these to only apply to the ones
>> I happen to be testing?
>> 
>> Thanks,
>> 
>> Barney
>> 
>> 
>> 
>> 
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