Is the C3 possible with SMP?

[Alexander Motin]

Alexandre "Sunny" Kovalenko wrote:
>> I have tried to enable C3 state on my Core2Duo laptop and found that it 
>> is not working good. System HZ timer stops during CPU sleep. After some 
>> investigation I have found that it is due to LAPIC timer used for HZ 
>> stopped during C3 state (same as during AMD's C1E).
>>
>> So the question is: Is it possible (or planned) to make it work somehow? 
>> For example, by using some external timer instead of LAPIC's one?
>>
>> ACPI reports about 20% less idle power consumption with C3 state 
>> comparing to C2. It would be interesting to get additional half an hour 
>> on battery.
>>
> You can get half way there by adding
> 
> dev.cpu.1.cx_lowest=C3
> 
> to /etc/sysctl.conf

Thanks.

1. Looks like it does not kill the timer.
2. I haven't got any benefit from it in idle state. According to 
`acpiconf -i 0` I have about 13 Amps (IMHO more looks like Watts) with 
both C2 and this half-to-C3, but only 11 Amps in full C3 (but without 
timer).
3. I have got about 10% benefit (33 Amps against 36) when cpu0 is 100% 
busy while cpu1 is idle.

-- 
Alexander Motin