performance by endian

[Adrian Chadd]

Hi,

1c is DQS delay tap control byte 0 (DDR D0..D7); 20 is DQS delay tap
control byte 1 (DDR D8..D15.)

0xf is:

4:0 TAP_L 0x5 Tap setting for lower 32-level delay chain for both registers.

It's to do with DDR timing. We'd have to look at the DDR2 chip and the
config path to see what the appropriate values are.



-adrian


On 23 August 2017 at 21:27, Mori Hiroki <yamori813 at yahoo.co.jp> wrote:
> Hi
>
> AR9331 is ONION OMEGA. This module have Winbond W9751G6KB
> DDR2 memory.
>
>
> I checked AR9331 DDR TAP register at boot time.
>
> TAP_CONTROL_0(0x1800001c) = 0xf
> TAP_CONTROL_1(0x18000020) = 0x10 of 0xf
>
> I think this is ar7240_ddr_ap_init() result in u-boot code.
>
> I don't know what is TAP. But is this relation to this
> problem ?
>
> Hiroki Mori
>
> ----- Original Message -----
>> From: Adrian Chadd <adrian.chadd at gmail.com>
>> To: Mori Hiroki <yamori813 at yahoo.co.jp>
>> Cc: "freebsd-mips at freebsd.org" <freebsd-mips at freebsd.org>
>> Date: 2017/8/15, Tue 06:10
>> Subject: Re: performance by endian
>>
>> hm, which DDR bus does it have?
>>
>>
>>
>> -adrian
>>
>>
>> On 25 July 2017 at 19:09, Mori Hiroki <yamori813 at yahoo.co.jp> wrote:
>>>  Hi
>>>
>>>
>>>  Sorry I talk about AR9331 soc.
>>>
>>>  I check boot log.
>>>
>>>  RT3050 is this.
>>>
>>>
>>>  Cache info:
>>>    picache_stride    = 4096
>>>    picache_loopcount = 8
>>>    pdcache_stride    = 4096
>>>    pdcache_loopcount = 4
>>>  cpu0: MIPS Technologies processor v76.150
>>>    MMU: Standard TLB, 32 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes)
>>>    L1 i-cache: 4 ways of 256 sets, 32 bytes per line
>>>    L1 d-cache: 4 ways of 128 sets, 32 bytes per line
>>>    L2 cache: disabled
>> Config1=0xbea3319e<PerfCount,WatchRegs,MIPS16,EJTAG>
>>>    Config2=0x80000000
>>>    Config3=0x420
>>>
>>>  AR9331 is this.
>>>
>>>  Cache info:
>>>    picache_stride    = 4096
>>>    picache_loopcount = 16
>>>    pdcache_stride    = 4096
>>>    pdcache_loopcount = 8
>>>    max line size     = 32
>>>  cpu0: MIPS Technologies processor v116.147
>>>    MMU: Standard TLB, 16 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes)
>>>    L1 i-cache: 4 ways of 512 sets, 32 bytes per line
>>>    L1 d-cache: 4 ways of 256 sets, 32 bytes per line
>>>    L2 cache: disabled
>>>    Config1=0x9ee3519e<PerfCount,WatchRegs,MIPS16,EJTAG>
>>>    Config2=0x80000000
>>>    Config3=0x20
>>>    Config7=0x0
>>>
>>>  I seem AR9331 have more cache than RT3050.
>>>
>>>  awk script is this.
>>>
>>>  BEGIN {
>>>      printf "%d¥n", fib(32)
>>>  }
>>>
>>>  function fib(n) {
>>>      if (n < 2) return n
>>>      return fib(n - 2) + fib(n - 1)
>>>  }
>>>
>>>  ----- Original Message -----
>>>>  From: Adrian Chadd <adrian.chadd at gmail.com>
>>>>  To: Mori Hiroki <yamori813 at yahoo.co.jp>
>>>>  Cc: "freebsd-mips at freebsd.org"
>> <freebsd-mips at freebsd.org>
>>>>  Date: 2017/7/26, Wed 02:14
>>>>  Subject: Re: performance by endian
>>>>
>>>>  well, how much cache, how much out-of-order is it? The AR9330 SoC has
>>>>  very limited cache :(
>>>>
>>>>
>>>>
>>>>  -adrian
>>>>
>>>>
>>>>  On 24 July 2017 at 00:53, Mori Hiroki <yamori813 at yahoo.co.jp>
>> wrote:
>>>>>   Hi.
>>>>>
>>>>>   I checked fib(32) by awk script.
>>>>>
>>>>>   RT3050 is 80 sec
>>>>>   AR9330 is 99 sec
>>>>>
>>>>>
>>>>>   AR9330 is newer and clock is hight. But slow.
>>>>>
>>>>>   Why this result ?
>>>>>
>>>>>   I suspect this is endian issue.
>>>>>
>>>>>   I have problem mruby performance at Atheros SOC.
>>>>>   It is slow almost double from same clock little
>>>>>   endian mips soc.
>>>>>
>>>>>   Regards
>>>>>
>>>>>   Hiroki Mori
>>>>>   _______________________________________________
>>>>>   freebsd-mips at freebsd.org mailing list
>>>>>   https://lists.freebsd.org/mailman/listinfo/freebsd-mips
>>>>>   To unsubscribe, send any mail to
>>>>  "freebsd-mips-unsubscribe at freebsd.org"
>>>>
>>