interrupt muxes, bus memory space and other fun amusing things

[Adrian Chadd]

Well i'm happy to do it in two pieces:

* do whatever to get it up and working so I can do the rest of the qca
mips bringups so we get access to like 50 new routers that are out
there right now;
* take the mips, ppc and arm bits and drive home the unified front,
now that we have all the pieces in place and things work.



-adrian


On 5 January 2015 at 19:26, Warner Losh <imp at bsdimp.com> wrote:
>
>> On Jan 5, 2015, at 8:14 PM, Ian Lepore <ian at FreeBSD.org> wrote:
>>
>> On Mon, 2015-01-05 at 20:10 -0700, Warner Losh wrote:
>>>> On Jan 5, 2015, at 1:31 PM, Adrian Chadd <adrian at FreeBSD.org> wrote:
>>>>
>>>> On 5 January 2015 at 08:41, Warner Losh <imp at bsdimp.com> wrote:
>>>>>
>>>>>> So if I were Linux, I'd just implement a mux that pretends to trigger
>>>>>> interrupts in a much bigger IRQ space. Ie, they map IP0..IP7 to
>>>>>> irq0..7, then they pick another IRQ range for the AHB interrupts, and
>>>>>> another IRQ range for the IP2/IP3 interrupt mux. They have a
>>>>>> hard-coded mux that takes care of triggering the software IRQ based on
>>>>>> the hardware interrupt and mux register contents.
>>>>>>
>>>>>> So, how should I approach this?
>>>>>
>>>>> Same way. You’d create an interrupt device that registers an interrupt
>>>>> for the mux, then farms it out based on the contents of the registers.
>>>>> The MIPS interrupt handler might need some work (arm did) to
>>>>> allow this to happen, but it isn’t super difficult (though IIRc it is tedious).
>>>>
>>>> Ok. So I can do that, but then devices hang off of which bus? nexus0?
>>>> Or this mux?
>>>>
>>>> Can I create a mux bus to hang things off of that just pass all the
>>>> memory region requests up to the parent bus (nexus in this case) ?
>>>
>>> The hard part is mapping an interrupt provided by a mux to a resource
>>> number. However, we already do this for the ‘hard wired’ interrupts
>>> that are muxed through APIC or PIC controllers on x86. I fail to see how
>>> this is any different, apart (perhaps) from the need to do things dynamically
>>> in some way.
>>>
>>> Warner
>>>
>>
>> It sounds like mips is ready for intrng.  Which would then give us ppc,
>> arm, and mips all with a conceptually-similar intrng-like layer for
>> handling non-hierarchical interrupt sources and controllers and mapping
>> between rman and hardware ideas of interrupt number.  Hmmm.  This would
>> be the time to argue for a nice shiny new MI intrng implementation...
>> except that we can't quite drive even the arm-only version to
>> completion.
>
> Maybe now’s the time?
>
> Warner