L2 cache management and busdma - or, "damnit USB, who you not like me"

[Adrian Chadd]

hi,

It shouldn't be - the atheros mips doesn't have l2 cache.

I wish I could reproduce your issue. :(



-a


On 21 December 2015 at 21:09, Eugene Grosbein <eugen at grosbein.net> wrote:
> On 21.12.2015 12:02, Adrian Chadd wrote:
>> hi,
>>
>> I've been poking at the ci20 port to bring it up to
>> self-booting/running, and this involves using USB1 as a rootfs. Yeah,
>> I know, ohci, but that's what I have for now.
>>
>> Anyway, there was filesystem corruption, so I went digging into it and
>> found that we just weren't taking L2 cache line size into account when
>> doing the busdma bits. The JZ4780 SoC has 32 byte L1 lines, and 128
>> byte L2 lines. Oops
>>
>> So, two things are needed:
>>
>> * for the ci20 port, which isn't in the mainline tree yet, we need to
>> use USB_HOST_ALIGN=128, and
>> * we need to teach the busdma code about the maximum line size, not
>> just the L1 line size.
>>
>> Here's a diff that does the latter:
>>
>> https://people.freebsd.org/~adrian/mips/mips-fix-dcache-busdma.diff
>>
>> I'm going to test this out on my L1-only platforms (read: atheros) tomorrow.
>>
>> Does anyone have any comments?
>
> Can that be the source of my USB problems? Total system hang while doing lots of umass I/O
> with TP-Link TL-WDR3600? If yes, I'd like to re-run my tests with these new patches.
>