How's bus-space stuff supposed to work with superscalar MIPS?

[Stanislav Sedov]

On Oct 5, 2013, at 10:18 AM, Adrian Chadd <adrian at freebsd.org> wrote:

> Hi all,
> 
> I've been bringing up the AR9344 PHY and after a lot of digging, I
> discovered that I can fix things by changing ARGE_WRITE() (ie, write to the
> ethernet space registers) to:
> 
> bus_write_4();
> bus_read_4();
> 
> .. to (what I'm guessing here) flush the write out before the next
> instruction is run.
> 
> So, given this particular hilarity has shown up, what's the story with
> doing IO accesses on a superscalar MIPS CPU? If it's going to kseg1, is it
> somehow going to magically enforce ordering? Or am I right in thinking we
> will need explicit barriers here?
> 

I don't know specifics of mips74k, but usually one indeed needs memory barriers
when performing read of write operation sequences that require ordering on
device I/O (e.g changing the ring and writing the new ring index afterwards).  I would
not be surprised if the cpu reorders i/o bus memory access, especially a multi-issue
one.

It is a good idea to have barriers where needed regardless.  We have special macros
for them which are defined to nothing on the in-order platforms.