svn commit: r225892 - head/sys/mips/mips

[Andrew Duane]

An assert, or some other check would work. Could you just add "EndWaitSkip - StartWaitSkip" somehow? I just worry that some day it won't be 16 bytes any more....

 ...................................
Andrew Duane
Juniper Networks
o   +1 978 589 0551
m  +1 603-770-7088
aduane at juniper.net

 


> -----Original Message-----
> From: c.jayachandran at gmail.com [mailto:c.jayachandran at gmail.com] On
> Behalf Of Jayachandran C.
> Sent: Tuesday, October 04, 2011 10:48 AM
> To: Andrew Duane
> Cc: Warner Losh; Adrian Chadd; Kostik Belousov; Alexander Motin;
> freebsd-mips at freebsd.org
> Subject: Re: svn commit: r225892 - head/sys/mips/mips
> 
> On Tue, Oct 4, 2011 at 9:34 PM, Andrew Duane <aduane at juniper.net>
> wrote:
> > The MIPS manual volume 3 says there is a 3 cycle "typical" wait
> between an MTC0 that messes with Status[IE] and an interrupted
> instruction. That hazard doesn't seem to apply here, to any of the
> cases we have.
> >
> > I do have a question: in StartWaitSkip, the value of Status[IE] is
> being toggled, not cleared. Is that correct? Do we always guarantee
> that it will be set on entry here?
> 
> Interrupts have to be enabled in cpu_idle(), there is an assert in the
> beginning of cpu_idle which checks this.
> 
> > I had also made a comment about the "PTR_ADDU k1, 16    # skip over
> wait" in MipsKernIntr; I think it would be safer (and clearer) to do
> "PTR_LA        k1, EndWaitSkip" instead.
> 
> Loading an immediate address takes more instructions (esp in 64 bit)
> adding 16 is just one instruction.  I should really add an KASSERT
> somewhere to make sure that EndWaitSkip - StartWaitSkip is 16...
> 
> JC.