svn commit: r225892 - head/sys/mips/mips

[Andrew Duane]

Let me pull my MIPS manual when I get in. It exactly specifies the hazards for each bit.

Warner Losh <imp at bsdimp.com> wrote:


On Oct 3, 2011, at 7:38 PM, Adrian Chadd wrote:

> On 4 October 2011 07:09, Andrew Duane <aduane at juniper.net> wrote:
>> The COP0_SYNC's should be there (should there also be one after the MTC0 in MipsKernIntr?). The ISA says a hazard is needed, so that should be reflected. I assume different platforms define COP0_SYNC for themselves as needed?
>
> Is one needed after the mtc0 after StartWaitSkip?

I don't think it matters.  The COP0_SYNC is needed when you want to flush the instruction pipeline so that changes to COP0 don't affect them 'randomly'.  However, in this case.  Either we're setting a bit that's already set, which won't change anything, or we're setting a bit that's clear, which will just delay the delivery of the interrupt a few cycles.  The race where it happens before the wait instruction is handled by the rest of the patch.

Warner