Diffs to fix L1 cache flush problems

[Neelkanth Natu]

Hi,

This is a simple change that fixes problems invalidating L1 
data/instruction caches. The problem is that the type of the variable
that holds the size of the instruction/data caches is uint8_t. Clearly
this is going to overflow.

On the Sibyte with 32KB cache size the uint8_t was causing it to be 
truncated to 0. This in turn makes the cache flush routines turn into
no-ops.

I ran into this when testing kernel loadable modules and have verified that
this change fixes the problem.

best
Neel

==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/include/cpuinfo.h#2 (text) - //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/include/cpuinfo.h#3 (text) ==== content
@@ -57,11 +57,11 @@
 	u_int16_t	tlb_nentries;
 	u_int8_t	icache_virtual;
 	struct {
-		u_int8_t	ic_size;
+		unsigned int	ic_size;
 		u_int8_t	ic_linesize;
 		u_int8_t	ic_nways;
 		u_int16_t	ic_nsets;
-		u_int8_t	dc_size;
+		unsigned int	dc_size;
 		u_int8_t	dc_linesize;
 		u_int8_t	dc_nways;
 		u_int16_t	dc_nsets;