Diffs to fix L1 cache flush problems

[Oleksandr Tymoshenko]

Neelkanth Natu wrote:
> Hi,
> 
> This is a simple change that fixes problems invalidating L1 
> data/instruction caches. The problem is that the type of the variable
> that holds the size of the instruction/data caches is uint8_t. Clearly
> this is going to overflow.
> 
> On the Sibyte with 32KB cache size the uint8_t was causing it to be 
> truncated to 0. This in turn makes the cache flush routines turn into
> no-ops.
> 
> I ran into this when testing kernel loadable modules and have verified that
> this change fixes the problem.
     Thanks, committed.