i386 cpu_reset_real: code/comment mismatch

[Andriy Gapon]

This is not a real issue, just a code clarification.

First a snippet from sys/i386/i386/vm_machdep.c, cpu_reset_real()
/*
 * Attempt to force a reset via the Reset Control register at
 * I/O port 0xcf9.  Bit 2 forces a system reset when it is
 * written as 1.  Bit 1 selects the type of reset to attempt:
 * 0 selects a "soft" reset, and 1 selects a "hard" reset.  We
 * try to do a "soft" reset first, and then a "hard" reset.
 */
outb(0xcf9, 0x2);
outb(0xcf9, 0x6);

I think that the comment is correct up to but not including the last
sentence. Writing 0x2 sets bit 1 to 1 (thus selecting hard reset), and
writing 0x6 sets both bits 2 and 1 to 1 (thus performing hard reset).
So we always just do a hard reset, no trying of soft reset (would it
even make sense to do the last line of the comment says).

-- 
Andriy Gapon