ECC support

[Igor Mozolevsky]

On 16 September 2015 at 12:34, Bob Bishop <rb at gid.co.uk> wrote:

<snip>


> "The best we can conclude therefore is that any chip size effect is
> unlikely to dominate error rates given that the trends are not consistent
> across various other confounders such as age and manufacturer.”
>
> I’ll admit to talking that point up a bit but it is counterintuitive.
> Memory designers have always been scared of cosmic rays etc but the
> suspected effects simply have not been noticeable. Most likely as they
> shrink features ever smaller, other factors like material purity dominate.
>

I saw that after I posted, and had a long ponder as to why it would be so.
The only thing I could think of is that the fab process was(/is?) large
enough to not worry about "nonsense" like cosmic rays &c (but then I've not
had much exposure to semi-conductor electronics theory since late 90s).
Perhaps we're at a point where the fab process can't really shrink much
more with DRAM due to the underlying tech (effectively many tiny RC
circuits), which is the reason the manufacturers just stack ranks to get
more capacity per DIMM instead of packing more in a single chip?..


-- 
Igor M.