PCIe transaction size

[Hartmut Brandt]

Hi all,

I'm designing a FPGA board that has memory that is accessible via the PCIe 
bus from FreeBSD. I observed, that the host always splits the memory 
transactions on 8 byte boundaries. So reading or storing an 128-bit 
integer generates two transactions, if the integer is unaligned even four.

Is there a way to get the CPU or chipset or whoever produces the 
transactions to make larger transactions? I found an Intel paper that 
seems to talk about this (How to Implement a 64B PCIe Burst Transfer or 
Intel Architecture) but I've no idea how to do what they write on FreeBSD 
:-).

Any help?

harti