Weird PCI interrupt delivery problem (resolution, sort of)

[Scott Long]

John Baldwin wrote:
> On Tuesday 24 January 2006 19:34, Craig Boston wrote:
> 
>>On Tue, Jan 24, 2006 at 10:43:49AM -0500, John Baldwin wrote:
>>
>>>What if you do a read of the lapic before the write?  Maybe doing 'x =
>>>lapic->eoi;  lapic->eoi = 0;'?
>>
>>Reading the lapic before the write has no effect.
>>
>>Reading the lapic after the write makes it work.
> 
> 
> Hmm, perhaps the read forces the write to post?  Scott?
> 

Either that, or the read imposes enough delay to let whatever was
happening during the DELAY call work.   I find it hard to believe that
uncached writes would get delayed like this.  I've lost the original
posting on this, could you provide the dmesg and computer make/model
again?

Scott