Possible instruction pipelining problem between HT's on the same die ?

[John-Mark Gurney]

Matthew Dillon wrote this message on Fri, Jun 03, 2005 at 13:57 -0700:
>     I've been tracking down a crash one of our users gets occassionally.
>     He has a quad Intel(R) XEON(TM) CPU 2.00GHz (1996.61-MHz 686-class CPU)
>     system.
> 
>     After getting a few of these crashes he pulled three of the four cpus
>     out.   But with just one physical cpu, with HTT turned on (so two
>     logical cpus), he is still getting these crashes.
> 
>     This is the sequence that causes the bad data:
> 
>     cpu #0	write A
> 		write B
> 
>     (HT)cpu #1	read B
> 		if (B) 
> 		    read A	<----  gets OLD data in A, not new data

[...]

>     I looked at the various SFENCE/LFENCE/MFENCE instructions and they
>     do not seem to guarentee ordering for speculative accesses at all.
>     They all say that they do not protect against speculative reads.
>     Bus-locked instructions don't seem to avoid speculative reads either.

have you put a SFENCE between write A and write B?  You never tell us
where you've tried to put the various fence instructions...

-- 
  John-Mark Gurney				Voice: +1 415 225 5579

     "All that I will do, has been done, All that I have, has not."