Determining CPU features / cache organization from userland

[Bruce M Simpson]

On Fri, Oct 10, 2003 at 03:09:47PM -0400, Andrew Gallatin wrote:
> Bruce M Simpson writes:
>  > I've been thinking we should definitely make the cache organization
>  > info available via sysctl. I am thinking we should do this to make
>  > the UMA_ALIGN_CACHE definition mean something...
> 
> If you do this,  it may make sense to use the same names as MacOSX.
> 
> Eg: 
> 
> g51% sysctl hw | grep cache
> hw.cachelinesize: 128
> hw.l1icachesize: 65536
> hw.l1dcachesize: 32768
> hw.l2cachesize: 524288

Er, that's weird, considering POWER has the CLCS instruction which is
intended to support variable cache line sizes. Doesn't POWER4 and POWER5
have a cache which is split in this way?

Also can we assume they are the same for all CPUs in an SMP system? I'd
like to think that that is the case.

BMS