vmware2 patch for -CURRENT

[Andrew Gallatin]

Bruce Evans writes:
 > On Mon, 3 May 2004, Andrew Gallatin wrote:
 > > It panics in sse2_pagezero() on my p4, so I have to break into
 > > the debugger and reduce my cpu_class to 3.  I"m really glad that the
 > > jsnap builds have ddb built in.. ;)
 > 
 > Apparently vmware2 doesn't support some SSE2 instructions despite claiming
 > to.  The code that calls ss2_pagezero() seems to test mostly the right
 > things.  (cpu_feature & CPU_SSE2) is supposed to indicate that the CPU
 > supports SSE2, and it shouldn't be necessary to also test cpu_class.
 > 
 > Try my memory access benchmarks in ~bde/cache on freefall for debugging
 > this in userland (./w -c sse2 -f 19 uses the same access method as
 > sse2_pagezero()).

Weird.  It works in userspace:

% ./bde_w -c sse2 -f 19
zeroJ: 2637193597 B/s (  37919 us) (122532576 tsc) (movnti)

The generic kernel dies at sse2_pagezero+0xe with a 

    Fatal trap 1: priviliged instruction fault while in kernel mode

According to gdb's disassemble, its the movnti:

(gdb) disassemble sse2_pagezero
Dump of assembler code for function sse2_pagezero:
0xc0757e04 <sse2_pagezero>:     push   %ebx
0xc0757e05 <sse2_pagezero+1>:   mov    0x8(%esp,1),%ecx
0xc0757e09 <sse2_pagezero+5>:   mov    %ecx,%eax
0xc0757e0b <sse2_pagezero+7>:   add    $0x1000,%eax
0xc0757e10 <sse2_pagezero+12>:  xor    %ebx,%ebx
0xc0757e12 <sse2_pagezero+14>:  movnti %ebx,(%ecx)
0xc0757e15 <sse2_pagezero+17>:  add    $0x4,%ecx
0xc0757e18 <sse2_pagezero+20>:  cmp    %ecx,%eax
0xc0757e1a <sse2_pagezero+22>:  jne    0xc0757e12 <sse2_pagezero+14>
0xc0757e1c <sse2_pagezero+24>:  sfence 
0xc0757e1f <sse2_pagezero+27>:  pop    %ebx
0xc0757e20 <sse2_pagezero+28>:  ret    
0xc0757e21 <sse2_pagezero+29>:  lea    0x0(%esi),%esi

Drew