nand controller - how should one handle controllers that want the command+address bits together?

[Adrian Chadd]

On 18 March 2014 07:12, Warner Losh <imp at bsdimp.com> wrote:

> Because the state machines needed for different NAND types more or
> less require the 'low level' interface that we have today. The different
> phases in setting up a transaction vary somewhat between the different
> types of NAND, and we have no real knowledge of that in the NAND layer
> today. It was written 4 years ago when most controllers on the market
> did little more than bit-bang and/or module the signals to the NAND since
> the interfaces at the time were little more than fancy memory mapped
> memory controllers.

Right.


> I've also been looking towards this area as well, given my recent
> NAND history. In fact, I've been putting together a talk for BSDcan
> on what needs to be done to make the NAND layer sane, cool and
> groovy.

I may have to come to bsdcan then.

You have a DB120; take a look at the ar934x-nfc.c code in openwrt and
see what they do.

There's apparently a PIO mechanism. It's unclear how to use it and
honestly I wouldn't want to.


-a