nand controller - how should one handle controllers that want the command+address bits together?

[Warner Losh]

On Mar 18, 2014, at 5:35 AM, Adrian Chadd <adrian at FreeBSD.org> wrote:

> Hiya,
> 
> I've got the atheros ar934x nand controller bits looking like they're
> working on freebsd-head enough to send/receive a READID command with
> an address of 0x0. However, the NAND controller sends commands with
> the cmd and address phases as part of the command, rather than calling
> send_command / send_address methods called multiple times.
> 
> It seems like our nandbus and nand controller layer is a very thin
> shim over what the NAND control messages look like, rather than some
> higher level 'thing' that allows for slightly more intelligent (read:
> DMA/ECC capable) hardware.
> 
> So, what gives?

Our NAND layer is very thin. The early controllers that were targeted by the NAND
controller were rather dump, little more than bit-bang controllers that could
modulate ALE and CLE as needed. There’s no provision for DMA, at all really.
There’s very little provision for ECC, since that’s usually done as part of the DMA
operation.

I’m surprised you haven’t complained about the excruciatingly long busy waits yet.
Our complete ignoring of the B/NR signal. The lack of any kind of interrupt attempts
for the GPIO pins we’re driving, the hardwired state machines for the NAND that just
happen to work with the older generation parts but will encounter issues on the latest
NAND.

Warner