TL-WR1043: switch

[Stefan Bethke]

Am 30.11.2011 um 20:58 schrieb Warner Losh:

> On Nov 30, 2011, at 12:43 PM, Stefan Bethke wrote:
> 
>> The I2C framework makes a faulty assumption that the read/not-write bit of the first byte (the address) indicates whether reads or writes are to follow.  While many simple I2C devices usually will follow this rule, it's not prescribed by the protocol (AFAICT), and is incompatible with the way the RTL8366 familiy uses the bus: after sending the address+read/not-write byte, two register address bytes are sent, then the 16-bit register value is sent or received.  While the register write access can be performed as a 4-byte write, the read access requires the read bit to be set, but the first two bytes for the register address then need to be transmitted.
> 
> I thought that was spelled out in the i2c spec fairly clearly…

You are of course correct.

>  Do you have the data sheet showing this timing?

I don't have one for the 8366RB, but the 8366 and 8366S chips appear to follow the same timing.  See 
http://realtek.info/pdf/rtl8366_8369_datasheet_1-1.pdf (9.2, page 44)
http://realtek.info/pdf/rtl8366s_8366sr_datasheet_vpre-1.4_20071022.pdf (9.2, page 66)

I think it would be beneficial to either remove this constraint in iicconf.c entirely, or make it optional, so that we can use the infrastructure for devices that "almost" speak I2C.


Stefan

-- 
Stefan Bethke <stb at lassitu.de>   Fon +49 151 14070811