TL-WR1043: switch

[Stefan Bethke]

Am 13.12.2011 um 11:02 schrieb Adrian Chadd:

> On 12 December 2011 23:54, Stefan Bethke <stb at lassitu.de> wrote:
>>> Does the arge0 "phy" map to a specific switch port phy, for general
>>> configuration and status? Or is it totally separate here (requiring
>>> configuration of rtl8366rb0portX ?)
>> 
>> There is no PHY connected to arge0, just the switch MAC.  I believe the RTL8366RB configures the CPU port (port 5) through pin strapping on power up.  My code only return the current configuration, but does not allow you to change it.
> 
> Ok. So what's arge0's PHY configuration coming from? Or is it being
> handled as a multi-phy, where it forces speed/duplex (and MAC PLL +
> MII clock but I have to fix that for ar71xx/ar724x) and then just
> nails the port as always up, rather than binding a phy instance to it?

It's hard-wired on both ends, the PHY MAC and the arge MAC.


Stefan

-- 
Stefan Bethke <stb at lassitu.de>   Fon +49 151 14070811