ar71xx_gpio.c touches SPI_CS1 and 2?

[Adrian Chadd]

On 4 December 2011 21:59, Stefan Bethke <stb at lassitu.de> wrote:

>> I'm pretty sure the SPI flash is actually being talked to via
>> bitbanged GPIO, rather than the actual ar71xx/ar91xx SPI interface.
>> So those chip selects aren't strictly needed.

>
> I couldn't tell.  The register definitions in ar71xxreg.h seem to indicate that there is hardware support for SPI, and that CS1 and CS2 (but not CS0) share the pins with GPIO, but looking at the code in ar71xx_spi.c seems to do bit banging for transmit and register read for reception.  Does the SPI support only have a shift register for reception?

I'm wrong. ar71xx_spi.c actually does use the SPI block.

Ask me about that after mid-december. I have the atheros SoC
datasheets; I just have no time to figure it out. Maybe ask ray@, he
also has access to these datasheets now.
(No we can't give them out. Yes, you can sign an NDA with Qualcomm
Atheros to get access to some of this documentation.)

> Hhm.
>
> How about the ar71xx_spi.c driver claiming CS0 and optionally CS1 and CS2 (again via hint?), and setting the GPIO function bits accordingly?  Or only activate CS1 and CS2 if we have SPI bus children that claim them?

Let's just have a hint that says "claim CS1 / claim CS2" for the
ar71xx spi code. I think that'll be enough.
We can then get rid of that function_enable call in ar71xx_gpio.c.

The trick here is making sure we properly lock access to the function
register? :)


Adrian