First cut at hwpmc support on MIPS

[Joseph Koshy]

> > 7) From the definitions in the header file, these PMCs appear to
> >   support the concept of sampling based on processor mode:
> > 
> > +#define MIPS_PMC_USER_ENABLE           0x08    /* Count in USER mode */
> > +#define MIPS_PMC_SUPER_ENABLE          0x04    /* Count in SUPERVISOR mode */
> > +#define MIPS_PMC_KERNEL_ENABLE         0x02    /* Count in KERNEL mode */
> > 
> >   If that is the case, then you should support those modifiers in
> >   libpmc's event parsing.  The libpmc code in the patch appears to be
> >   a stub:
> > 
> > +static int
> > +mips_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
> > +                 struct pmc_op_pmcallocate *pmc_config __unused)
> > +{
> > +       switch (pe) {
> > +       default:
> > +               break;
> > +       }
> > +       
> > +       return (0);
> > +}
> > 
> > 
> Is there any other processor that does this?  Right now I make the chip
> sample in all modes by fiat.

All the Intel and AMD PMCs: see the handling of the "usr" and "os"
qualifiers.

> > 8) You can reduce the size of the following table in "hwpmc_mips.c",
> >   by treating the pe_counter field as a set of flags.
> > 
> > +struct mips_event_code_map {
> > +       enum pmc_event  pe_ev;      /* enum value */
> > +       uint8_t         pe_counter; /* Which counter this can be counted in. */
> > +       uint8_t         pe_code;    /* numeric code */
> > +};
> > 
> > +const struct mips_event_code_map mips_event_codes[] = {
> > +       { PMC_EV_MIPS_CYCLE, 0, 0},
> > +       { PMC_EV_MIPS_CYCLE, 1, 0},  <<<--- repeated information 

Most Intel CPUs have restrictions on the events that PMCs support.
You may want to look at the P6, or Intel Core support code for examples.

> > 9) You'd want to support flags that control counting based on
> >   processor modes.  For this, you would want to pass down flags
> >   from userland and change the `pm_mips_evsel' field to suit:
> > 
> > +static int
> > +mips_allocate_pmc(int cpu, int ri, struct pmc *pm,
> > +  const struct pmc_op_pmcallocate *a)
> > +{
> > ...
> > +       pm->pm_md.pm_mips.pm_mips_evsel = config;
> > 

> Again, for both of these, is there an example I should work from?

See P6, Pentium IV, AMD, Intel Core for examples.

Additional comments on patch #3:

 * The manual page still has UTF 8.  E.g.,-
+Count all pipeline bubbles that are a result of multicycle ISPRAM
+access. Pipeline bubbles are defined as all cycles that IFU doesn<E2><80><99>t
+present an instruction to ALU. The four cycles after a redirect are
 * The convention is that sentences always start on a new line in
   -mdoc input.


Regards,
Koshy