npe(4) closet cleaning

[Bruce Simpson]

Hi,

Here is a patch I found I needed with the Freecom FSG3 to get  other PHY 
drivers to attach.

I have not committed it because it's strictly development code at the 
moment.

cheers
BMS
-------------- next part --------------
Index: sys/arm/xscale/ixp425/if_npe.c
===================================================================
--- sys/arm/xscale/ixp425/if_npe.c	(revision 186036)
+++ sys/arm/xscale/ixp425/if_npe.c	(working copy)
@@ -83,6 +83,8 @@
 
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
+#include "miidevs.h"
+
 #include <arm/xscale/ixp425/if_npereg.h>
 
 #include "miibus_if.h"
@@ -140,6 +142,9 @@
 	struct npestats	*sc_stats;
 	bus_dmamap_t	sc_stats_map;
 	bus_addr_t	sc_stats_phys;	/* phys addr of sc_stats */
+	int		sc_force_bmsr;
+	int		sc_force_idr1;
+	int		sc_force_idr2;
 };
 
 /*
@@ -244,6 +249,8 @@
 static uint32_t	npe_getimageid(struct npe_softc *);
 static int	npe_setloopback(struct npe_softc *, int ena);
 #endif
+static int	npe_miibus_readreg(device_t dev, int phy, int reg);
+static void	npe_miibus_writereg(device_t dev, int phy, int reg, int data);
 
 /* NB: all tx done processing goes through one queue */
 static int tx_doneqid = -1;
@@ -733,6 +740,18 @@
 	if (!override_unit(dev, "phy", &sc->sc_phy, 0, MII_NPHY-1))
 		sc->sc_phy = npeconfig[unit].phy;
 
+	/*
+	 * Allow PHY OUI/model and BMSR to be forced, as some boards have
+	 * a PHY which does not have ID registers (e.g. the RTL8305SB
+	 * on a Freecom FSG3).
+	 */
+	if (!override_unit(dev, "force_bmsr", &sc->sc_force_bmsr, 0, 0xFFFF))
+		sc->sc_force_bmsr = 0;
+	if (!override_unit(dev, "force_idr1", &sc->sc_force_idr1, 0, 0xFFFF))
+		sc->sc_force_idr1 = 0;
+	if (!override_unit(dev, "force_idr2", &sc->sc_force_idr2, 0, 0xFFFF))
+		sc->sc_force_idr2 = 0;
+
 	KASSERT(npes[npeconfig[unit].npeid] == NULL,
 	    ("npe %u already setup", npeconfig[unit].npeid));
 	npes[npeconfig[unit].npeid] = sc;
@@ -1598,6 +1617,14 @@
 
 	if (phy != sc->sc_phy)		/* XXX no auto-detect */
 		return 0xffff;
+
+	if (reg == MII_BMSR && sc->sc_force_bmsr != 0x0000)
+		return (sc->sc_force_bmsr);
+	if (reg == MII_PHYIDR1 && sc->sc_force_idr1 != 0x0000)
+		return (sc->sc_force_idr1);
+	if (reg == MII_PHYIDR2 && sc->sc_force_idr2 != 0x0000)
+		return (sc->sc_force_idr2);
+
 	v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)
 	  | NPE_MII_GO;
 	npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v);
@@ -1605,6 +1632,7 @@
 		v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS);
 	else
 		v = 0xffff | NPE_MII_READ_FAIL;
+
 	return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff);
 #undef MAXTRIES
 }
@@ -1617,6 +1645,7 @@
 
 	if (phy != sc->sc_phy)		/* XXX */
 		return;
+
 	v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL)
 	  | data | NPE_MII_WRITE
 	  | NPE_MII_GO;