Leaving the Desktop Market

[Allan Jude]

On 05/12/2014 22:09, Allan Jude wrote:
> 
> Will try to grab results from a few more machines
> 
> 
> _______________________________________________
> freebsd-current at freebsd.org mailing list
> http://lists.freebsd.org/mailman/listinfo/freebsd-current
> To unsubscribe, send any mail to "freebsd-current-unsubscribe at freebsd.org"
> 


>From my laptop:

#pcm.x 1

 Intel(r) Performance Counter Monitor V2.6 (2013-11-04 13:43:31 +0100
ID=db05e43)

 Copyright (c) 2009-2013 Intel Corporation

Number of physical cores: 2
Number of logical cores: 4
Threads (logical cores) per physical core: 2
Num sockets: 1
Core PMU (perfmon) version: 3
Number of core PMU generic (programmable) counters: 4
Width of generic (programmable) counters: 48 bits
Number of core PMU fixed counters: 3
Width of fixed counters: 48 bits
Nominal core frequency: 2600000000 Hz
Package thermal spec power: 35 Watt; Package minimum power: 24 Watt;
Package maximum power: 0 Watt;

Detected Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz "Intel(r)
microarchitecture codename Ivy Bridge"

 EXEC  : instructions per nominal CPU cycle
 IPC   : instructions per CPU cycle
 FREQ  : relation to nominal CPU frequency='unhalted clock
ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
 AFREQ : relation to nominal CPU frequency while in active state (not in
power-saving C state)='unhalted clock ticks'/'invariant timer ticks
while in C0-state'  (includes Intel Turbo Boost)
 L3MISS: L3 cache misses
 L2MISS: L2 cache misses (including other core's L2 cache *hits*)
 L3HIT : L3 cache hit ratio (0.00-1.00)
 L2HIT : L2 cache hit ratio (0.00-1.00)
 L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in
some cases could be >1.0 due to a higher memory latency
 L2CLK : ratio of CPU cycles lost due to missing L2 cache but still
hitting L3 cache (0.00-1.00)
 READ  : bytes read from memory controller (in GBytes)
 WRITE : bytes written to memory controller (in GBytes)
 TEMP  : Temperature reading in 1 degree Celsius relative to the TjMax
temperature (thermal headroom): 0 corresponds to the max temperature


 Core (SKT) | EXEC | IPC  | FREQ  | AFREQ | L3MISS | L2MISS | L3HIT |
L2HIT | L3CLK | L2CLK  | READ  | WRITE | TEMP

   0    0     0.00   0.84   0.00    0.46     295 K    564 K    0.48
0.21    0.55    0.11     N/A     N/A     60
   1    0     0.00   0.77   0.00    0.46     166 K    279 K    0.40
0.24    0.62    0.10     N/A     N/A     60
   2    0     0.00   0.75   0.00    0.46     138 K    200 K    0.31
0.29    0.46    0.05     N/A     N/A     60
   3    0     0.00   0.78   0.00    0.46     170 K    249 K    0.32
0.28    0.50    0.05     N/A     N/A     60
-------------------------------------------------------------------------------------------------------------------
 SKT    0     0.00   0.80   0.00    0.46     770 K   1294 K    0.40
0.24    0.53    0.08    0.11    0.04     60
-------------------------------------------------------------------------------------------------------------------
 TOTAL  *     0.00   0.80   0.00    0.46     770 K   1294 K    0.40
0.24    0.53    0.08    0.11    0.04     N/A

 Instructions retired:  208 M ; Active cycles:  261 M ; Time (TSC):   25
Gticks ; C0 (active,non-halted) core residency: 0.55 %

 C1 core residency: 4.44 %; C3 core residency: 0.16 %; C6 core
residency: 94.85 %; C7 core residency: 0.00 %;
 C2 package residency: 4.26 %; C3 package residency: 0.10 %; C6 package
residency: 88.28 %; C7 package residency: 0.00 %;

 PHYSICAL CORE IPC                 : 1.60 => corresponds to 39.89 %
utilization for cores in active state
 Instructions per nominal CPU cycle: 0.00 => corresponds to 0.10 % core
utilization over time interval
----------------------------------------------------------------------------------------------

----------------------------------------------------------------------------------------------
 SKT    0 package consumed 23.02 Joules
----------------------------------------------------------------------------------------------
 TOTAL:                    23.02 Joules