Leaving the Desktop Market
Allan Jude
freebsd at allanjude.com
Tue May 13 02:46:38 UTC 2014
On 05/12/2014 22:12, Allan Jude wrote:
> On 2014-05-12 14:25, Adrian Chadd wrote:
>> Just run intel-pcm and see. Thanks, -a
>
> Not sure if this is expected or not, but on
>
> Intel(R) Core(TM) i5-3570 CPU @ 3.40GHz
>
>
> all of the pcm.x tools just hang (cpu state: usem)
>
>
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Found the problem
The first time I tried to run pcm.x it crashed (because I didn't have
cpuctl kldloaded). On my laptop this gave a friendly error, but on the
desktop i5 it just signal 8'd.
Anyway, removing the stale lock file, /tmp/SEMDIntel_PCM_inst_lock
resolved it
#pcm.x 10
Intel(r) Performance Counter Monitor V2.6 (2013-11-04 13:43:31 +0100
ID=db05e43)
Copyright (c) 2009-2013 Intel Corporation
Number of physical cores: 4
Number of logical cores: 4
Threads (logical cores) per physical core: 1
Num sockets: 1
Core PMU (perfmon) version: 3
Number of core PMU generic (programmable) counters: 8
Width of generic (programmable) counters: 48 bits
Number of core PMU fixed counters: 3
Width of fixed counters: 48 bits
Nominal core frequency: 3400000000 Hz
Package thermal spec power: 77 Watt; Package minimum power: 60 Watt;
Package maximum power: 0 Watt;
Detected Intel(R) Core(TM) i5-3570 CPU @ 3.40GHz "Intel(r)
microarchitecture codename Ivy Bridge"
EXEC : instructions per nominal CPU cycle
IPC : instructions per CPU cycle
FREQ : relation to nominal CPU frequency='unhalted clock
ticks'/'invariant timer ticks' (includes Intel Turbo Boost)
AFREQ : relation to nominal CPU frequency while in active state (not in
power-saving C state)='unhalted clock ticks'/'invariant timer ticks
while in C0-state' (includes Intel Turbo Boost)
L3MISS: L3 cache misses
L2MISS: L2 cache misses (including other core's L2 cache *hits*)
L3HIT : L3 cache hit ratio (0.00-1.00)
L2HIT : L2 cache hit ratio (0.00-1.00)
L3CLK : ratio of CPU cycles lost due to L3 cache misses (0.00-1.00), in
some cases could be >1.0 due to a higher memory latency
L2CLK : ratio of CPU cycles lost due to missing L2 cache but still
hitting L3 cache (0.00-1.00)
READ : bytes read from memory controller (in GBytes)
WRITE : bytes written to memory controller (in GBytes)
TEMP : Temperature reading in 1 degree Celsius relative to the TjMax
temperature (thermal headroom): 0 corresponds to the max temperature
Core (SKT) | EXEC | IPC | FREQ | AFREQ | L3MISS | L2MISS | L3HIT |
L2HIT | L3CLK | L2CLK | READ | WRITE | TEMP
0 0 0.00 0.21 0.02 0.49 1532 K 2978 K 0.49
0.01 0.43 0.08 N/A N/A 73
1 0 0.00 0.29 0.00 0.98 119 K 208 K 0.43
0.12 0.30 0.05 N/A N/A 73
2 0 0.00 0.29 0.00 1.00 117 K 169 K 0.31
0.12 0.33 0.03 N/A N/A 73
3 0 0.00 0.39 0.00 0.93 131 K 162 K 0.19
0.18 0.32 0.02 N/A N/A 73
-------------------------------------------------------------------------------------------------------------------
SKT 0 0.00 0.24 0.01 0.56 1900 K 3518 K 0.46
0.03 0.40 0.07 0.19 0.02 73
-------------------------------------------------------------------------------------------------------------------
TOTAL * 0.00 0.24 0.01 0.56 1900 K 3518 K 0.46
0.03 0.40 0.07 0.19 0.02 N/A
Instructions retired: 200 M ; Active cycles: 850 M ; Time (TSC): 34
Gticks ; C0 (active,non-halted) core residency: 1.12 %
C1 core residency: 1.76 %; C3 core residency: 0.10 %; C6 core
residency: 97.02 %; C7 core residency: 0.00 %;
C2 package residency: 43.01 %; C3 package residency: 0.13 %; C6 package
residency: 41.23 %; C7 package residency: 0.00 %;
PHYSICAL CORE IPC : 0.24 => corresponds to 5.89 %
utilization for cores in active state
Instructions per nominal CPU cycle: 0.00 => corresponds to 0.04 % core
utilization over time interval
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
SKT 0 package consumed 69.21 Joules
----------------------------------------------------------------------------------------------
TOTAL: 69.21 Joules
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