[Bug 221733] SSE2 instructions emited in compiler-rt on AMD Sempron 3000+

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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=221733

            Bug ID: 221733
           Summary: SSE2 instructions emited in compiler-rt on AMD Sempron
                    3000+
           Product: Base System
           Version: 10.3-STABLE
          Hardware: i386
                OS: Any
            Status: New
          Severity: Affects Only Me
          Priority: ---
         Component: bin
          Assignee: freebsd-bugs at FreeBSD.org
          Reporter: bsdpr at phoe.frmug.org

On an i386 host using an AMD Sempron 3000+ CPU the compiler-rt include at least
one SSE2 instruction which is not supported by that CPU.

Boot log CPU identification:

CPU: AMD Sempron(tm)   3000+ (1999.82-MHz 686-class CPU)
  Origin="AuthenticAMD"  Id=0x6a0  Family=0x6  Model=0xa  Stepping=0
 
Features=0x383fbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,MMX,FXSR,SSE>
  AMD Features=0xc0480800<SYSCALL,MP,MMX+,3DNow!+,3DNow!>

Excerpt from objdump -d /usr/lib/libcompiler-rt.a:

floatdidf.o:     file format elf32-i386-freebsd

Disassembly of section .text:

00000000 <twop52>:
   0:   00 00                   add    %al,(%eax)
   2:   00 00                   add    %al,(%eax)
   4:   00 00                   add    %al,(%eax)
   6:   30 43 00                xor    %al,0x0(%ebx)

00000008 <twop32>:
   8:   00 00                   add    %al,(%eax)
   a:   00 00                   add    %al,(%eax)
   c:   00 00                   add    %al,(%eax)
   e:   f0 41                   lock inc %ecx

00000010 <__floatdidf>:
  10:   f2 0f 2a 4c 24 08       cvtsi2sd 0x8(%esp),%xmm1
  16:   f3 0f 10 44 24 04       movss  0x4(%esp),%xmm0
  1c:   e8 00 00 00 00          call   21 <__floatdidf+0x11>
  21:   58                      pop    %eax
  22:   f2 0f 59 88 e7 ff ff    mulsd  -0x19(%eax),%xmm1
  29:   ff
  2a:   f2 0f 10 90 df ff ff    movsd  -0x21(%eax),%xmm2
  31:   ff
  32:   f2 0f 5c ca             subsd  %xmm2,%xmm1
  36:   66 0f 56 c2             orpd   %xmm2,%xmm0
  3a:   f2 0f 58 c1             addsd  %xmm1,%xmm0
  3e:   f2 0f 11 44 24 04       movsd  %xmm0,0x4(%esp)
  44:   dd 44 24 04             fldl   0x4(%esp)
  48:   c3                      ret

The first instruction of __floatdidf, cvtsi2sd, is not supported by that CPU.
World and kernel were built on that same host from svn revision 320864.

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