Rock64 clock errors following r354558

[Peter Jeremy]

Hi Michal,

Somewhere between r354439 and r354592, my Rock64 (RK3328) has started
reporting errors setting the clocks on aclk_bus_pre and aclk_peri_pre.
My best guess is that it's somewhere in r354554..r354558.  I have had
a quick look and noting jumps out at me so I'm wondering if you have
any ideas.

The relevant non-verbose messages are now:
rk3328_cru0: <Rockchip RK3328 Clock and Reset Unit> mem 0xff440000-0xff440fff on ofwbus0
rk3328_cru0: cannot get parent at idx 6
Cannot set frequency for clk: aclk_bus_pre, error: 34
rk3328_cru0: Failed to set aclk_bus_pre to a frequency of 15000000
Cannot set frequency for clk: aclk_peri_pre, error: 34
rk3328_cru0: Failed to set aclk_peri_pre to a frequency of 15000000

The "cannot get parent" has been around for as long as I can tell but
the "cannot set frequency" errors are both new.

Looking back, my previous verbose boot was at r354239 and it shows:
rk3328_cru0: cannot get assigned clock at idx 5
rk3328_cru0: cannot get parent at idx 6
rk3328_cru0: Set aclk_bus_pre to 15000000
rk3328_cru0: Set aclk_peri_pre to 15000000
rk3328_cru0: cannot get assigned clock at idx 8

With a verbose boot at r354607 (including some additional debug printf's),
it now shows:
rk3328_cru0: cannot get assigned clock at idx 5
rk3328_cru0: cannot get parent for aclk_bus_pre at idx 6
rk_clk_composite_set_freq:(aclk_bus_pre)Finding best parent/div for target freq of 15000000
rk_clk_composite_set_freq:(aclk_bus_pre)Testing with parent cpll (0) at freq 594000000
rk_clk_composite_set_freq:(aclk_bus_pre)Testing with parent gpll (1) at freq 576000000
rk_clk_composite_set_freq:(aclk_bus_pre)Best divisor is 0
Cannot set frequency for clk: aclk_bus_pre, error: 34
rk_clk_composite_recalc:(aclk_bus_pre)Read: muxdiv_offset=100, val=2501
rk_clk_composite_recalc:(aclk_bus_pre)parent_freq=576000000, div=6
rk_clk_composite_recalc:(aclk_bus_pre)Final freq=96000000
rk_clk_composite_recalc:(hclk_bus_pre)Read: muxdiv_offset=104, val=1113
rk_clk_composite_recalc:(hclk_bus_pre)parent_freq=96000000, div=2
rk_clk_composite_recalc:(hclk_bus_pre)Final freq=48000000
rk_clk_composite_recalc:(pclk_bus_pre)Read: muxdiv_offset=104, val=1113
rk_clk_composite_recalc:(pclk_bus_pre)parent_freq=96000000, div=2
rk_clk_composite_recalc:(pclk_bus_pre)Final freq=48000000
rk3328_cru0: Failed to set aclk_bus_pre to a frequency of 15000000
rk_clk_composite_set_freq:(aclk_peri_pre)Finding best parent/div for target freq of 15000000
rk_clk_composite_set_freq:(aclk_peri_pre)Testing with parent cpll (0) at freq 594000000
rk_clk_composite_set_freq:(aclk_peri_pre)Testing with parent gpll (1) at freq 576000000
rk_clk_composite_set_freq:(aclk_peri_pre)Best divisor is 0
Cannot set frequency for clk: aclk_peri_pre, error: 34
rk_clk_composite_recalc:(aclk_peri_pre)Read: muxdiv_offset=170, val=4143
rk_clk_composite_recalc:(aclk_peri_pre)parent_freq=576000000, div=4
rk_clk_composite_recalc:(aclk_peri_pre)Final freq=144000000
rk_clk_composite_recalc:(pclk_peri)Read: muxdiv_offset=0, val=40c8
rk_clk_composite_recalc:(pclk_peri)parent_freq=144000000, div=1
rk_clk_composite_recalc:(pclk_peri)Final freq=144000000
rk_clk_composite_recalc:(hclk_peri)Read: muxdiv_offset=0, val=40c8
rk_clk_composite_recalc:(hclk_peri)parent_freq=144000000, div=5
rk_clk_composite_recalc:(hclk_peri)Final freq=28800000
rk3328_cru0: Failed to set aclk_peri_pre to a frequency of 15000000
rk3328_cru0: cannot get assigned clock at idx 8

-- 
Peter Jeremy
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