BPi-M3's A83T: "socket" 0 and "socket" 1 (clusters 0 and 1): how difficult/messy to enable use of both?

[Mark Millard]

I attempted a boot of a BPi-M3 (A83T based) via a linux image and I noted that the boot sequence reported:

[    0.040298] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.040383] Setting up static identity map for 0x4076b5a8 - 0x4076b600
[    0.010000] CPU1: Booted secondary processor
[    0.010000] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.010000] CPU2: Booted secondary processor
[    0.010000] CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
[    0.010000] CPU3: Booted secondary processor
[    0.010000] CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
[    0.260089] CPU4: failed to boot: -22
[    0.300067] CPU5: failed to boot: -22
[    0.340070] CPU6: failed to boot: -22
[    0.380092] CPU7: failed to boot: -22
[    0.380310] Brought up 4 CPUs
[    0.380335] SMP: Total of 4 processors activated (19200.00 BogoMIPS).
. . . [somewhat later in the sequence] . . .
[    0.010000] CPU4: Booted secondary processor
[    0.010000] CPU4: thread -1, cpu 0, socket 1, mpidr 80000100
[    0.010000] CPU5: Booted secondary processor
[    0.010000] CPU5: thread -1, cpu 1, socket 1, mpidr 80000101
[    0.010000] CPU6: Booted secondary processor
[    0.010000] CPU6: thread -1, cpu 2, socket 1, mpidr 80000102
[    0.010000] CPU7: Booted secondary processor
[    0.010000] CPU7: thread -1, cpu 3, socket 1, mpidr 80000103

[I'll note that all 8 cores are of the same type (cortex-a7) for the A83T: This is not an arm big/LITTLE context mixing core types but a more symmetric form of NUMA(?), more like sockets with the same type of multi-core processor in each socket and no cache spanning across the sockets, although RAM does span the "sockets" for the A83T.]

This suggests that the linux folks made the two clusters of cores in the A83T (Allwinner's A83T_User_Manual_v1.5.1_20150513.pdf terminology ) fit into the linux socket handling structure (a.k.a. NUMA structure, I presume). (About 29 pages of the 547 page A83T_User_Manual_v1.5.1_20150513.pdf mention "cluster", mostly for details of the clusters' various control, status, mask, gating, and power registers.)


Not that I consider it likely to be reasonable but I'll ask: How likely is it that someone could be given various pointers and bootstrap themselves into possibly enabling such dual-cluster usage for the A83T to a useful degree in FreeBSD? How independent of other SOC/board details would the effort/result be (given that the A83T is what is in use)? Would there be some sequence of stages to the effort? (The details would probably be part of the pointers that I mentioned. . .)



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Mark Millard
markmi at dsl-only.net