current meaning of BUS_DMA_COHERENT

[John Wehle]

On Mar 20, 2015, at 8:27 AM, Ian Lepore <ian at freebsd.org> wrote:
> The main problem is shared concurrent-access memory, such as buffer
> descriptor rings which are accessed simultaneously by the cpu and
> network hardware.  (The same thing happens with other hardware, but NICs
> are the prime example of it.)
> ...
> What we really need is a new type of busdma memory (BUS_DMA_DESCRIPTOR)
> and a special sync call to use in conjunction with it that takes an
> offset and length, and the sync is a single operation, no pre/post
> stuff.

If you have descriptor A being modified by the device at the same time
descriptor B is modified by the CPU and they are in the same cache line
you'll still have problems even with a sync call which takes an offset
and length.

Doesn't being able to sync individual descriptors also require padding the
descriptor size so it's a multiple of the cache line size?

-- John