Performance issues with raspberry pi 2

[Ian Lepore]

On Wed, 2015-07-15 at 17:58 +0200, Hans Petter Selasky wrote:
> On 05/18/15 00:02, Daisuke Aoyama wrote:
> >
> > Previous subset does not work correctly in ratecheck.
> > I don't know a reason but same code from ODROID-C1 version works.
> > I re-create the patch as dwc_otg-rpi2-20150518.patch.
> >
> > http://www.peach.ne.jp/archives/rpi/patch/dwc_otg-rpi2-20150518.patch
> 
> Hi,
> 
> I've finally had time to look at your patch, and it has some clever new 
> ideas to optimise the DWC OTG performance. I like it and will do some 
> work to integrate your patches like promised this week. It might be too 
> late for the coming 10.x release, but will for sure hit 10-stable when 
> the next 10.x is out. Thank you!
> 
> One question though: Are the WMB's and RMB's strictly needed? Isn't the 
> I/O memory mapped coherently?
> 
> Did you consider enabling the TXFIFOEMPTY IRQs instead of spinning?

I've been saying for years that you cannot assume that COHERENT means
"no sync operations needed", and that's more true than ever with armv6.

It is especially true of DEVICE mappings for arm memory-mapped IO: the
region is uncached and inelligible for write-combining, but write access
is still buffered (and dmb()/dsb() is insufficient to ensure that the
write buffers are flushed on all hardware; bus_space_barrier() does the
right thing).

Using inline barriers like that in bus_space IO code isn't right though;
that's what bus_space_barrier() is for.  Doing the barriers on every
bus_space access is probably overkill; typically when you need barriers
it's in a few specific places after a group of reads or writes, and
especially at places like the exit border in interrupt handling, or the
interlock points if interrupt handlers and non-interrupt code share
access to hardware registers.

-- Ian