[Differential] [Request, 91 lines] D3093: ARMv8 locore.S cleanup and TCR register update

[wma_semihalf.com (Wojciech Macek)]

wma_semihalf.com created this revision.
wma_semihalf.com added reviewers: zbb, emaste, andrew.
wma_semihalf.com added a subscriber: freebsd-arm-list.
wma_semihalf.com set the repository for this revision to rS FreeBSD src repository.
Herald added subscribers: emaste, andrew, imp.

REVISION SUMMARY
      This commit adds proper cache and shareability attributes to
      the TCR registers.
      Set memory attributes to Normal, outer and inner cacheable WBWA.
      Set shareability to inner and outer shareable when SMP is enabled.
      
      Also a locore file was cleaned up:
       - build_block_pagetables have an additional parameter added
         (shareability attribute) to allow mapping memory with other
         SH ATTR chosen if one wants to do so (like device SOC_DEV
         or similar)
      
      Fixes in locore.s:
       - opt_kstack_pages.h include was added to ensure the proper
         KSTACK_PAGES value is used
       - secondary stack calculation is modified to provide
         stack_top = secondary_stacks + (cpu_id)*PAGE_SIZE*KSTACK_PAGES
         because on ARMv8 the stack grows into lower memory addresses

REPOSITORY
  rS FreeBSD src repository

REVISION DETAIL
  https://reviews.freebsd.org/D3093

AFFECTED FILES
  sys/arm64/arm64/locore.S
  sys/arm64/include/armreg.h

EMAIL PREFERENCES
  https://reviews.freebsd.org/settings/panel/emailpreferences/

To: wma_semihalf.com, zbb, emaste, andrew
Cc: imp, andrew, freebsd-arm-list, emaste
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