BBB CPU clock (was: Re: FreeBSD on Cubieboard 2, UDOO and Galaxy Note 10.1 (Exynos).

[SAITOU Toshihide]

In message: <20131002.220051.226805883.toshi at ruby.ocn.ne.jp>
            SAITOU Toshihide <toshi at ruby.ocn.ne.jp> writes:
> I followed the steps you provided and my bbb (Rev A5A)
> booted at 912 MHz.

I forgot to mention details.

  DC power input 5V 1.2A or 5V 2.3A (no differences in
  result).

  BeagleBone Black, Rev A5A.

  TFTP boot and NFS root (currently).

  BEAGLEBONE kernel configuration or change it to include a
  beaglebone-black.dts. At the later needed to modify
  files.am335x to uncomment a line for ti_mmchs.c.


This is the most important that I forgot. I was using around
the head ALPHA3. I also tried ALPHA4 today and it doesn't
boot at high MPU frequency.

So, MPU frequency tolerance at boot is changed between
ALPHA3 and ALPHA4, more precisely from rev. 255931. That is,
it seems that it's more related to the software than DC
adaptor or PMIC power supply for now :-).

We may need stress2 at high frequency.


  cd /usr/src
  svn up -r 255930

  make buildkernel \
       TARGET=arm TARGET_ARCH=armv6 KERNCONF=BEAGLEBONE \
       WITH_FDT=yes >& buildkernel.log &

  cp /usr/obj/arm.armv6/usr/src/sys/BEAGLEBONE/kernel.bin \
     /tftpboot/beaglebone/boot/kernel/


Set MPU PLL to 912 MHz (390h),

  mw.l 0x44e00488 0x00000004
  mw.l 0x44e0042c 0x00039017
  mw.l 0x44e004a8 0x00000201
  mw.l 0x44e00488 0x00000007


Power supply for MPU (connected to DEFDCDC2) can control
from u-boot but has not close relation to the trerance of
the MPU clock within the appropriate value range.

  i2c mw 24 01 3f
  i2c mw 24 0b 72
  i2c mw 24 0f 11
  i2c mw 24 0b 72
  i2c mw 24 0f 11

  i2c md 24 0f 1

-- 
SAITOU Toshihide