Kernel Panic on DREAMPLUG: Alignment Fault 1
Mattia Rossi
mattia.rossi.mate at gmail.com
Thu Aug 1 16:14:09 UTC 2013
On 01/08/13 15:28, Ian Lepore wrote:
> On Thu, 2013-08-01 at 10:32 +0200, Mattia Rossi wrote:
>> <snip>
>>
>> Anyhow, I'll try to compile with gcc, and see what happens.
> The host system's compiler (gcc in your case) is used to build the
> selected compiler from src/, then that new compiler is used to build the
> rest of src/ into a runnable system. You can define WITHOUT_CLANG_IS_CC
> and WITHOUT_EABI to use gcc, and you should probably add WITHOUT_CLANG
> to avoid building it since it won't be used (and it takes forever to
> build).
Kernel built with gcc:
## Starting application at 0x00900000 ...
KDB: debugger backends: ddb
KDB: current backend: ddb
Copyright (c) 1992-2013 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
The Regents of the University of California. All rights reserved.
FreeBSD is a registered trademark of The FreeBSD Foundation.
FreeBSD 10.0-CURRENT #0 r253858M: Thu Aug 1 12:49:56 CEST 2013
root at freebsd9.1-base:/usr/obj/arm.arm/usr/devel/dreamplug/sys/DREAMPLUG-100m
gcc version 4.2.1 20070831 patched [FreeBSD]
WARNING: DIAGNOSTIC option enabled, expect reduced performance.
CPU: Feroceon 88FR131 rev 1 (Marvell core)
Little-endian DC enabled IC enabled WA disabled DC streaming enabled
BTB disabled L2 enabled L2 prefetch enabled
WB enabled EABT branch prediction enabled
16KB/32B 4-way instruction cache
16KB/32B 4-way write-back-locking-C data cache
real memory = 536870912 (512 MB)
avail memory = 511025152 (487 MB)
SOC: Marvell 88F6281 rev A1, TClock 200MHz
Instruction cache prefetch disabled, data cache prefetch disabled
256KB 4-way set-associative write-through unified L2 cache
random device not loaded; using insecure entropy
localbus0: <Marvell device bus> on fdtbus0
simplebus0: <Flattened device tree simple bus> on fdtbus0
ic0: <Marvell Integrated Interrupt Controller> mem 0xf1020200-0xf102023b
on sim0
timer0: <Marvell CPU Timer> mem 0xf1020300-0xf102032f irq 1 on simplebus0
Event timer "CPUTimer0" frequency 200000000 Hz quality 1000
Timecounter "CPUTimer1" frequency 200000000 Hz quality 1000
gpio0: <Marvell Integrated GPIO Controller> mem 0xf1010100-0xf101011f
irq 35,360
rtc0: <Marvell Integrated RTC> mem 0xf1010300-0xf1010307 on simplebus0
twsi0: <Marvell Integrated I2C Bus Controller> mem 0xf1011000-0xf101101f
irq 430
iicbus0: <Philips I2C bus> on twsi0
iic0: <I2C generic I/O> on iicbus0
mge0: <Marvell Gigabit Ethernet controller> mem 0xf1072000-0xf1073fff
irq 12,130
mge0: Ethernet address: f0:ad:4e:00:84:c7
miibus0: <MII bus> on mge0
e1000phy0: <Marvell 88E1116R Gigabit PHY> PHY 0 on miibus0
e1000phy0: none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX,
1000baseT, 10o
mge1: <Marvell Gigabit Ethernet controller> mem 0xf1076000-0xf1077fff
irq 16,170
mge1: Ethernet address: f0:ad:4e:00:84:c8
miibus1: <MII bus> on mge1
e1000phy1: <Marvell 88E1116R Gigabit PHY> PHY 1 on miibus1
e1000phy1: none, 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX,
1000baseT, 10o
uart0: <16550 or compatible> mem 0xf1012000-0xf101201f irq 33 on simplebus0
uart0: console (1056,n,8,1)
uart1: <16550 or compatible> mem 0xf1012100-0xf101211f irq 34 on simplebus0
cesa0: <Marvell Cryptographic Engine and Security Accelerator> mem
0xf1030000-00
ehci0: <Marvell Integrated USB 2.0 controller> mem 0xf1050000-0xf1050fff
irq 480
usbus0: EHCI version 1.0
usbus0: stop timeout
usbus0: set host controller mode
usbus0 on ehci0
mvs0: <Marvell 88F6281 SATA controller> mem 0xf1080000-0xf1085fff irq 21
on sim0
mvs0: Gen-IIe, 2 3Gbps ports, Port Multiplier supported with FBS
mvsch0: <Marvell SATA channel> at channel 0 on mvs0
mvsch1: <Marvell SATA channel> at channel 1 on mvs0
cryptosoft0: <software crypto>
Timecounters tick every 10.000 msec
IPsec: Initialized Security Association Processing.
ipfw2 (+ipv6) initialized, divert enabled, nat enabled, default to
accept, loggd
DUMMYNET 0 with IPv6 initialized (100409)
load_dn_sched dn_sched FIFO loaded
load_dn_sched dn_sched PRIO loaded
load_dn_sched dn_sched QFQ loaded
load_dn_sched dn_sched RR loaded
load_dn_sched dn_sched WF2Q+ loaded
Fatal kernel mode data abort: 'Alignment Fault 1'
trapframe: 0xde450d68
FSR=00000001, FAR=de450de4, spsr=60000093
r0 =10bec341, r1 =f1020300, r2 =0000001c, r3 =c34fe400
r4 =c0e68fe8, r5 =de450ddc, r6 =798ee230, r7 =00000015
r8 =c33ef400, r9 =00000000, r10=c0e4db78, r11=00000001
r12=c0e68bd4, ssp=de450db4, slr=c0d1bbd4, pc =c0aad40c
[ thread pid 0 tid 100035 ]
Stopped at binuptime+0x38: und 0xe1c580d8
db> bt
Tracing pid 0 tid 100035 td 0xc376f000
db_trace_self() at db_trace_self
pc = 0xc0d00484 lr = 0xc0d00510 (db_trace_thread+0x50)
sp = 0xde450a40 fp = 0x00000001
db_trace_thread() at db_trace_thread+0x50
pc = 0xc0d00510 lr = 0xc093f88c (db_command_init+0x618)
sp = 0xde450aa0 fp = 0x00000001
db_command_init() at db_command_init+0x618
pc = 0xc093f88c lr = 0xc093ef6c (db_skip_to_eol+0x484)
sp = 0xde450ab8 fp = 0x00000001
r4 = 0xc0e2b3f8 r5 = 0x00000000
db_skip_to_eol() at db_skip_to_eol+0x484
pc = 0xc093ef6c lr = 0xc093f0d4 (db_command_loop+0x5c)
sp = 0xde450b58 fp = 0x00000001
r4 = 0xde450b6c r5 = 0xc0e2b6c0
r6 = 0xde450de4 r7 = 0x00000000
r8 = 0x00000001 r10 = 0x600000d3
db_command_loop() at db_command_loop+0x5c
pc = 0xc093f0d4 lr = 0xc09414f8 (X_db_sym_numargs+0xec)
sp = 0xde450b60 fp = 0x00000001
X_db_sym_numargs() at X_db_sym_numargs+0xec
pc = 0xc09414f8 lr = 0xc0ad430c (kdb_trap+0xa4)
sp = 0xde450c78 fp = 0x00000001
r4 = 0xde450d68
kdb_trap() at kdb_trap+0xa4
pc = 0xc0ad430c lr = 0xc0d113c8 (badaddr_read+0x274)
sp = 0xde450c98 fp = 0x00000001
r4 = 0xde450d68 r5 = 0x00000001
r6 = 0xde450de4 r7 = 0xc376f000
r8 = 0xc33ef400 r10 = 0xde450d68
badaddr_read() at badaddr_read+0x274
pc = 0xc0d113c8 lr = 0xc0d11794 (prefetch_abort_handler+0x374)
sp = 0xde450cb0 fp = 0x00000001
r4 = 0xc376f000 r5 = 0xde450d68
r6 = 0x798ee230
prefetch_abort_handler() at prefetch_abort_handler+0x374
pc = 0xc0d11794 lr = 0xc0d118e4 (data_abort_handler+0x110)
sp = 0xde450cc8 fp = 0x00000001
r4 = 0xc0e8fb3c r5 = 0xffff1004
data_abort_handler() at data_abort_handler+0x110
pc = 0xc0d118e4 lr = 0xc0d01cc0 (exception_exit)
sp = 0xde450d68 fp = 0x00000001
r4 = 0xffffffff r5 = 0xffff1004
r6 = 0x798ee230 r7 = 0x00000015
r8 = 0xc33ef400 r9 = 0x00000000
r10 = 0xc0e4db78
exception_exit() at exception_exit
pc = 0xc0d01cc0 lr = 0xc0d1bbd4 (initarm_lastaddr+0x320)
sp = 0xde450db4 fp = 0x00000001
r0 = 0x10bec341 r1 = 0xf1020300
r2 = 0x0000001c r3 = 0xc34fe400
r4 = 0xc0e68fe8 r5 = 0xde450ddc
r6 = 0x798ee230 r7 = 0x00000015
r8 = 0xc33ef400 r9 = 0x00000000
r10 = 0xc0e4db78 r12 = 0xc0e68bd4
binuptime() at binuptime+0x3c
pc = 0xc0aad410 lr = 0xc0d26ac4 (cpu_initclocks+0xa8d8)
sp = 0xde450ddc fp = 0x00000000
r4 = 0xc0e9dc80 r5 = 0xc0e93518
r6 = 0x00000000 r7 = 0xc376f000
r8 = 0xc33ef400 r9 = 0x00000000
r10 = 0xde450e34
cpu_initclocks() at cpu_initclocks+0xa8d8
pc = 0xc0d26ac4 lr = 0xc0d1bdb8 (initarm_lastaddr+0x504)
sp = 0xde450dfc fp = 0x00000000
r4 = 0xc34fe400 r5 = 0xde450e34
initarm_lastaddr() at initarm_lastaddr+0x504
pc = 0xc0d1bdb8 lr = 0xc0a7ab5c (intr_event_handle+0x7c)
sp = 0xde450e04 fp = 0x00000000
r4 = 0xc3556ac0
intr_event_handle() at intr_event_handle+0x7c
pc = 0xc0a7ab5c lr = 0xc0d02f24 (arm_handler_execute+0x48)
sp = 0xde450e24 fp = 0x00000000
r4 = 0x00000001 r5 = 0xde450e34
r6 = 0x000003d7 r7 = 0xc0e8c8d0
r8 = 0xde450ea8 r9 = 0x00000000
r10 = 0x00000000
arm_handler_execute() at arm_handler_execute+0x48
pc = 0xc0d02f24 lr = 0xc0d173a0 (irq_entry+0x94)
sp = 0xde450e34 fp = 0x00000000
r4 = 0x00000000 r5 = 0xffff1004
irq_entry() at irq_entry+0x94
pc = 0xc0d173a0 lr = 0xc0d173a0 (irq_entry+0x94)
sp = 0xde450e34 fp = 0x00000000
More information about the freebsd-arm
mailing list