ARM/SMP, Some patches for review.
Łukasz Płachno
luk at semihalf.com
Mon Nov 19 15:28:07 UTC 2012
Hi,
I would like to propose few changes for ARM specific code.
Three attached patches for freebsd-current allows building SMP-safe
world for ARM targets and turns on TEX remap for ARMv6 and ARMv7 targets.
More details inside patch files.
Change introduced by "commit-2" removes armv7 targets (armv7 and pj4b)
from kernel.tramp.
AFAIK this feature is not working properly for armv7 targets and is
causing problem during compilation:
- LOCORE is defined during kernel compilation but not defined during
kernel.tramp compilation, so #include pmap.h causes build errors.
I do not think adding hack like this:
#ifndef LOCORE
#define LOCORE
#endif
to allow building something that is already broken is a good idea, so I
removed cpufunc_asm_pj4b.S and cpufunc_asm_armv7.S from Makefile.arm
Regards,
Łukasz Płachno
-------------- next part --------------
commit 4437ff36d8431819835c6777df239c5cc1932e7e
Author: Lukasz Plachno <luk at semihalf.com>
Date: Mon Nov 19 10:25:51 2012 +0100
arm: Cleanup in ARM specific code
- Unify descriptions for cache and TLB maintenance operations
- Use architecture macros instead of CPU specific ones in generic code
- Add memory barriers
- Remove armv7 targets from kernel.trampoline (not working currently),
add debug kernel map for build targets
diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S
index 58f295c..03561b8 100644
--- a/sys/arm/arm/cpufunc_asm_armv7.S
+++ b/sys/arm/arm/cpufunc_asm_armv7.S
@@ -71,9 +71,9 @@ ENTRY(armv7_setttb)
orr r0, r0, #PT_ATTR
mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */
#ifdef SMP
- mcr p15, 0, r0, c8, c3, 0 /* invalidate I+D TLBs Inner Shareable*/
+ mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */
#else
- mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
#endif
dsb
isb
@@ -82,11 +82,11 @@ ENTRY(armv7_setttb)
ENTRY(armv7_tlb_flushID)
dsb
#ifdef SMP
- mcr p15, 0, r0, c8, c3, 0 /* flush I+D tlb */
- mcr p15, 0, r0, c7, c1, 6 /* flush BTB */
+ mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */
+ mcr p15, 0, r0, c7, c1, 6 /* Flush BTB Inner Shareable */
#else
- mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
- mcr p15, 0, r0, c7, c5, 6 /* flush BTB */
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
+ mcr p15, 0, r0, c7, c5, 6 /* Flush BTB */
#endif
dsb
isb
@@ -96,10 +96,10 @@ ENTRY(armv7_tlb_flushID_SE)
ldr r1, .Lpage_mask
bic r0, r0, r1
#ifdef SMP
- mcr p15, 0, r0, c8, c3, 1 /* flush D tlb single entry Inner Shareable*/
+ mcr p15, 0, r0, c8, c3, 1 /* Invalidate I+D TLB single entry Inner Shareable */
mcr p15, 0, r0, c7, c1, 6 /* flush BTB Inner Shareable */
#else
- mcr p15, 0, r0, c8, c7, 1 /* flush D tlb single entry */
+ mcr p15, 0, r0, c8, c7, 1 /* Invalidate I+D TLB single entry Inner Shareable */
mcr p15, 0, r0, c7, c5, 6 /* flush BTB */
#endif
dsb
@@ -262,9 +262,9 @@ ENTRY(armv7_context_switch)
mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
#ifdef SMP
- mcr p15, 0, r0, c8, c3, 0 /* and flush the I+D tlbs Inner Sharable */
+ mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */
#else
- mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
#endif
dsb
isb
diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S
index 99b214a..3f803f1 100644
--- a/sys/arm/arm/locore.S
+++ b/sys/arm/arm/locore.S
@@ -172,7 +172,7 @@ Lunmapped:
mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
#endif
-#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
+#if defined(ARM_ARCH_6) || defined(ARM_ARCH_7A)
mov r0, #0
mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
#endif
@@ -182,7 +182,7 @@ Lunmapped:
mcr p15, 0, r0, c3, c0, 0
/* Enable MMU */
mrc p15, 0, r0, c1, c0, 0
-#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
+#if defined(ARM_ARCH_6) || defined(ARM_ARCH_7A)
orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
#endif
orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
@@ -371,7 +371,7 @@ Ltag:
mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
#endif
-#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
+#if defined(ARM_ARCH_6) || defined(ARM_ARCH_7A)
mov r0, #0
mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
#endif
@@ -383,7 +383,7 @@ Ltag:
mcr p15, 0, r0, c3, c0, 0
/* Enable MMU */
mrc p15, 0, r0, c1, c0, 0
-#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
+#if defined(ARM_ARCH_6) || defined(ARM_ARCH_7A)
orr r0, r0, #CPU_CONTROL_V6_EXTPAGE
#endif
orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE)
diff --git a/sys/arm/arm/machdep.c b/sys/arm/arm/machdep.c
index 17a60c2..11714da 100644
--- a/sys/arm/arm/machdep.c
+++ b/sys/arm/arm/machdep.c
@@ -834,7 +834,7 @@ fake_preload_metadata(struct arm_boot_params *abp __unused)
void
pcpu0_init(void)
{
-#if ARM_ARCH_6 || ARM_ARCH_7A || defined(CPU_MV_PJ4B)
+#if ARM_ARCH_6 || ARM_ARCH_7A
set_pcpu(pcpup);
#endif
pcpu_init(pcpup, 0, sizeof(struct pcpu));
diff --git a/sys/arm/include/atomic.h b/sys/arm/include/atomic.h
index 1a96176..f120191 100644
--- a/sys/arm/include/atomic.h
+++ b/sys/arm/include/atomic.h
@@ -47,9 +47,25 @@
#include <machine/cpuconf.h>
#endif
-#define mb()
-#define wmb()
-#define rmb()
+#if defined(ARM_ARCH_6) || defined(ARM_ARCH_7A)
+#define mb() do { \
+ uint32_t reg = 0; \
+ __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (reg)); \
+ } while (0)
+#define wmb() do { \
+ uint32_t reg = 0; \
+ __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (reg)); \
+ } while (0)
+#define rmb() do { \
+ uint32_t reg = 0; \
+ __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (reg)); \
+ } while (0)
+#else
+#define mb()
+#define wmb()
+#define rmb()
+#endif
+
#ifndef I32_bit
#define I32_bit (1 << 7) /* IRQ disable */
diff --git a/sys/conf/Makefile.arm b/sys/conf/Makefile.arm
index 6270aef..2f9e7ec 100644
--- a/sys/conf/Makefile.arm
+++ b/sys/conf/Makefile.arm
@@ -51,6 +51,7 @@ SYSTEM_LD_TAIL +=;sed s/" + SIZEOF_HEADERS"// ldscript.$M\
${SYSTEM_LD_}; \
${OBJCOPY} -S -O binary ${FULLKERNEL}.noheader \
${KERNEL_KO}.bin; \
+ ${NM} ${FULLKERNEL}.noheader | sort > ${FULLKERNEL}.map; \
rm ${FULLKERNEL}.noheader
.if defined(MFS_IMAGE)
@@ -63,7 +64,6 @@ FILES_CPU_FUNC = $S/$M/$M/cpufunc_asm_arm7tdmi.S \
$S/$M/$M/cpufunc_asm_xscale.S $S/$M/$M/cpufunc_asm.S \
$S/$M/$M/cpufunc_asm_xscale_c3.S $S/$M/$M/cpufunc_asm_armv5_ec.S \
$S/$M/$M/cpufunc_asm_fa526.S $S/$M/$M/cpufunc_asm_sheeva.S \
- $S/$M/$M/cpufunc_asm_pj4b.S $S/$M/$M/cpufunc_asm_armv7.S
KERNEL_EXTRA=trampoline
KERNEL_EXTRA_INSTALL=kernel.gz.tramp
-------------- next part --------------
commit 2888748d9134bbade8b8f607c6ec99f07093fad7
Author: Lukasz Plachno <luk at semihalf.com>
Date: Mon Nov 19 12:11:29 2012 +0100
arm: Implement new way for pagetable memory attributes management
- initialize PRRR and NMRR registers in cp15
- enable TEX remapping
- create macros for TTB attributes
- add PRRR and NMRR to show cp15 ddb command
diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index dd43c27..2a3acb4 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -2327,6 +2327,7 @@ pj4bv6_setup(char *args)
cpuctrl |= CPU_CONTROL_VECRELOC;
cpuctrl |= (0x5 << 16);
cpuctrl |= CPU_CONTROL_V6_EXTPAGE;
+ cpuctrl |= CPU_CONTROL_TEX_REMAP;
/* XXX not yet */
/* cpuctrl |= CPU_CONTROL_L2_ENABLE; */
@@ -2362,6 +2363,7 @@ pj4bv7_setup(args)
cpuctrl |= CPU_CONTROL_VECRELOC;
cpuctrl |= (0x5 << 16) | (1 < 22);
cpuctrl |= CPU_CONTROL_V6_EXTPAGE;
+ cpuctrl |= CPU_CONTROL_TEX_REMAP;
/* Clear out the cache */
cpu_idcache_wbinv_all();
@@ -2392,7 +2394,8 @@ cortexa_setup(char *args)
cpuctrl = CPU_CONTROL_MMU_ENABLE |
CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE |
- CPU_CONTROL_BPRD_ENABLE;
+ CPU_CONTROL_BPRD_ENABLE |
+ CPU_CONTROL_TEX_REMAP;
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
diff --git a/sys/arm/arm/cpufunc_asm_armv7.S b/sys/arm/arm/cpufunc_asm_armv7.S
index 03561b8..d6f9d59 100644
--- a/sys/arm/arm/cpufunc_asm_armv7.S
+++ b/sys/arm/arm/cpufunc_asm_armv7.S
@@ -32,6 +32,8 @@
#include <machine/asm.h>
__FBSDID("$FreeBSD$");
+#include <machine/pmap.h>
+
.cpu cortex-a8
.Lcoherency_level:
@@ -45,30 +47,13 @@ __FBSDID("$FreeBSD$");
.Lpage_mask:
.word 0xfff
-#define PT_NOS (1 << 5)
-#define PT_S (1 << 1)
-#define PT_INNER_NC 0
-#define PT_INNER_WT (1 << 0)
-#define PT_INNER_WB ((1 << 0) | (1 << 6))
-#define PT_INNER_WBWA (1 << 6)
-#define PT_OUTER_NC 0
-#define PT_OUTER_WT (2 << 3)
-#define PT_OUTER_WB (3 << 3)
-#define PT_OUTER_WBWA (1 << 3)
-
-#ifdef SMP
-#define PT_ATTR (PT_S|PT_INNER_WT|PT_OUTER_WT|PT_NOS)
-#else
-#define PT_ATTR (PT_INNER_WT|PT_OUTER_WT)
-#endif
-
ENTRY(armv7_setttb)
stmdb sp!, {r0, lr}
bl _C_LABEL(armv7_idcache_wbinv_all) /* clean the D cache */
ldmia sp!, {r0, lr}
dsb
- orr r0, r0, #PT_ATTR
+ orr r0, r0, #TTB_ATTR
mcr p15, 0, r0, c2, c0, 0 /* Translation Table Base Register 0 (TTBR0) */
#ifdef SMP
mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */
@@ -258,7 +243,7 @@ ENTRY(armv7_cpu_sleep)
ENTRY(armv7_context_switch)
dsb
- orr r0, r0, #PT_ATTR
+ orr r0, r0, #TTB_ATTR
mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
#ifdef SMP
diff --git a/sys/arm/arm/cpufunc_asm_pj4b.S b/sys/arm/arm/cpufunc_asm_pj4b.S
index f6890d9..f2eba94 100644
--- a/sys/arm/arm/cpufunc_asm_pj4b.S
+++ b/sys/arm/arm/cpufunc_asm_pj4b.S
@@ -33,6 +33,7 @@
__FBSDID("$FreeBSD$");
#include <machine/param.h>
+#include <machine/pmap.h>
.Lpj4b_cache_line_size:
.word _C_LABEL(arm_pdcache_line_size)
@@ -40,9 +41,7 @@ __FBSDID("$FreeBSD$");
ENTRY(pj4b_setttb)
/* Cache synchronization is not required as this core has PIPT caches */
mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */
-#ifdef SMP
- orr r0, r0, #2 /* Set TTB shared memory flag */
-#endif
+ orr r0, r0, #TTB_ATTR /* Set TTB memory flags */
mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
RET
@@ -199,4 +198,5 @@ ENTRY(pj4b_config)
orr r0, r0, #(1 << 5)
mcr p15, 0, r0, c1, c0, 1
#endif
+
RET
diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S
index 3f803f1..b09e202 100644
--- a/sys/arm/arm/locore.S
+++ b/sys/arm/arm/locore.S
@@ -38,6 +38,7 @@
#include <machine/asm.h>
#include <machine/armreg.h>
#include <machine/pte.h>
+#include <machine/pmap.h>
__FBSDID("$FreeBSD$");
@@ -162,8 +163,9 @@ Lunmapped:
orrne r5, r5, #PHYSADDR
movne pc, r5
-#if defined(SMP)
- orr r0, r0, #2 /* Set TTB shared memory flag */
+#if defined(ARM_ARCH_6) || defined(ARM_ARCH_7A)
+ /* For primary pagetable normal non-cacheable memory is used */
+ orr r0, r0, #TTB_FLAGS_2 /* Set TTB memory flags */
#endif
mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
#ifdef SMP
@@ -173,6 +175,17 @@ Lunmapped:
#endif
#if defined(ARM_ARCH_6) || defined(ARM_ARCH_7A)
+ /* Set PRRR and NMRR cp15 registers */
+ ldr r0, =PRRR
+ mcr p15, 0, r0, c10, c2, 0
+ ldr r0, =NMRR
+ mcr p15, 0, r0, c10, c2, 1
+
+ /* Set TEX Remap*/
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, #CPU_CONTROL_TEX_REMAP
+ mcr p15, 0, r0, c1, c0, 0
+
mov r0, #0
mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
#endif
@@ -257,7 +270,7 @@ mmu_init_table:
/* map VA 0xc0000000..0xc3ffffff to PA */
MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW))
MMU_INIT(0x48000000, 0x48000000, 1, L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW))
-#endif
+#endif /* SMP */
.word 0 /* end of table */
#endif
.Lstart:
@@ -361,8 +374,10 @@ Ltag:
bic r0, r0, #0xf0000000
orr r0, r0, #PHYSADDR
ldr r0, [r0]
-#if defined(SMP)
- orr r0, r0, #0 /* Set TTB shared memory flag */
+
+#if defined(ARM_ARCH_6) || defined(ARM_ARCH_7A)
+ /* For primary pagetable normal non-cacheable memory is used */
+ orr r0, r0, #TTB_FLAGS_2 /* Set TTB memory flags */
#endif
mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
#ifdef SMP
@@ -372,6 +387,17 @@ Ltag:
#endif
#if defined(ARM_ARCH_6) || defined(ARM_ARCH_7A)
+ /* Set PRRR and NMRR cp15 registers */
+ ldr r0, =PRRR
+ mcr p15, 0, r0, c10, c2, 0
+ ldr r0, =NMRR
+ mcr p15, 0, r0, c10, c2, 1
+
+ /* Set TEX Remap*/
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, #CPU_CONTROL_TEX_REMAP
+ mcr p15, 0, r0, c1, c0, 0
+
mov r0, #0
mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */
#endif
diff --git a/sys/arm/arm/mp_machdep.c b/sys/arm/arm/mp_machdep.c
index 30e6b63..7335adb 100644
--- a/sys/arm/arm/mp_machdep.c
+++ b/sys/arm/arm/mp_machdep.c
@@ -116,12 +116,12 @@ cpu_mp_start(void)
addr_end = (vm_offset_t)&_end - KERNVIRTADDR + KERNPHYSADDR;
addr_end &= ~L1_S_OFFSET;
addr_end += L1_S_SIZE;
- bzero((void *)temp_pagetable_va, L1_TABLE_SIZE);
+ bzero((void *)temp_pagetable_va, L1_TABLE_SIZE);
for (addr = KERNPHYSADDR; addr <= addr_end; addr += L1_S_SIZE) {
((int *)(temp_pagetable_va))[addr >> L1_S_SHIFT] =
L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr;
((int *)(temp_pagetable_va))[(addr -
- KERNPHYSADDR + KERNVIRTADDR) >> L1_S_SHIFT] =
+ KERNPHYSADDR + KERNVIRTADDR) >> L1_S_SHIFT] =
L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW)|L1_S_DOM(PMAP_DOMAIN_KERNEL)|addr;
}
temp_pagetable = (void*)(vtophys(temp_pagetable_va));
diff --git a/sys/arm/arm/pmap-v6.c b/sys/arm/arm/pmap-v6.c
index a44bdbf..a01ef45 100644
--- a/sys/arm/arm/pmap-v6.c
+++ b/sys/arm/arm/pmap-v6.c
@@ -386,34 +386,45 @@ static struct vm_object pvzone_obj;
static int pv_entry_count=0, pv_entry_max=0, pv_entry_high_water=0;
static struct rwlock pvh_global_lock;
+#if defined(SMP)
+#define L1_SHAREABLE L1_SHARED
+#define L2_SHAREABLE L2_SHARED
+#else
+#define L1_SHAREABLE 0
+#define L2_SHAREABLE 0
+#endif /* SMP */
+
int l1_mem_types[] = {
- ARM_L1S_STRONG_ORD,
- ARM_L1S_DEVICE_NOSHARE,
- ARM_L1S_DEVICE_SHARE,
- ARM_L1S_NRML_NOCACHE,
- ARM_L1S_NRML_IWT_OWT,
- ARM_L1S_NRML_IWB_OWB,
- ARM_L1S_NRML_IWBA_OWBA
+ (L1_SHAREABLE),
+ (L1_SHAREABLE | L1_S_B),
+ (L1_SHAREABLE | L1_S_C),
+ (L1_SHAREABLE | L1_S_C | L1_S_B),
+ (L1_SHAREABLE | L1_S_TEX(1)),
+ (L1_SHAREABLE | L1_S_TEX(1) | L1_S_B),
+ (L1_SHAREABLE),
+ (L1_SHAREABLE | L1_S_TEX(1) | L1_S_C | L1_S_B)
};
int l2l_mem_types[] = {
- ARM_L2L_STRONG_ORD,
- ARM_L2L_DEVICE_NOSHARE,
- ARM_L2L_DEVICE_SHARE,
- ARM_L2L_NRML_NOCACHE,
- ARM_L2L_NRML_IWT_OWT,
- ARM_L2L_NRML_IWB_OWB,
- ARM_L2L_NRML_IWBA_OWBA
+ (L2_SHAREABLE),
+ (L2_SHAREABLE | L2_B),
+ (L2_SHAREABLE | L2_C),
+ (L2_SHAREABLE | L2_C | L2_B),
+ (L2_SHAREABLE | L2_L_TEX(1)),
+ (L2_SHAREABLE | L2_L_TEX(1) | L2_B),
+ (L2_SHAREABLE),
+ (L2_SHAREABLE | L2_L_TEX(1) | L2_C | L2_B)
};
int l2s_mem_types[] = {
- ARM_L2S_STRONG_ORD,
- ARM_L2S_DEVICE_NOSHARE,
- ARM_L2S_DEVICE_SHARE,
- ARM_L2S_NRML_NOCACHE,
- ARM_L2S_NRML_IWT_OWT,
- ARM_L2S_NRML_IWB_OWB,
- ARM_L2S_NRML_IWBA_OWBA
+ (L2_SHAREABLE),
+ (L2_SHAREABLE | L2_B),
+ (L2_SHAREABLE | L2_C),
+ (L2_SHAREABLE | L2_C | L2_B),
+ (L2_SHAREABLE | L2_S_TEX(1)),
+ (L2_SHAREABLE | L2_S_TEX(1) | L2_B),
+ (L2_SHAREABLE),
+ (L2_SHAREABLE | L2_S_TEX(1) | L2_C | L2_B)
};
/*
diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h
index 05b3846..f5ccfb9 100644
--- a/sys/arm/include/armreg.h
+++ b/sys/arm/include/armreg.h
@@ -286,6 +286,7 @@
#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */
#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */
+#define CPU_CONTROL_TEX_REMAP 0x10000000 /* TEX Remap enabled */
#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
diff --git a/sys/arm/include/pmap.h b/sys/arm/include/pmap.h
index e20bf18..d7b42b8 100644
--- a/sys/arm/include/pmap.h
+++ b/sys/arm/include/pmap.h
@@ -52,33 +52,127 @@
#include <machine/pte.h>
#include <machine/cpuconf.h>
+
/*
- * Pte related macros
+ * When TEX remap is enabled (SCTLR.TRE is set to 1),
+ * PRRR and NMRR values needs to be initialized before MMU is used.
+ *
+ * TEX[0],C,B -> index(n)
+ *
+ * PMRR -> memory type (strongly ordered, device, normal), shareability
+ * TR (PRRR[2n+1:2n]) -> memory type
+ * NOS (PRMRR[24+n]) -> non outer shareable attribute
+ * DS0 (PRRR[16]) -> device memory shareable attribute (S = 0)
+ * DS1 (PRRR[17]) -> device memory shareable attribute (S = 1)
+ * NS0 (PRRR[18]) -> normal memory shareable attribute (S = 0)
+ * NS1 (PRRR[19]) -> normal memory shareable attribute (S = 1)
+ *
+ * NMRR -> cache policy (no cache, WT, WB, WBWA)
+ * IR (NMRR[2n+1;2n]) -> inner cache property
+ * OR (NMRR[2n+17;2n+16]) -> outer cache property
+ *
+ * Memory type index TR IR OR
+ * STRONGLY_ORDERED 0 00
+ * DEVICE 1 01
+ * NOCACHE 2 10 00 00
+ * IWT_OWT 3 10 10 10
+ * IWB_OWB 4 10 11 11
+ * IWBA_OWBA 5 10 01 01
+ * RESERVED 6
+ * IWBA_OWB 7 10 01 11
+ *
+ * Other attributes:
+ * DS0 = 0
+ * DS1 = 1
+ * NS0 = 0
+ * NS1 = 1
+ *
+ * Outer shareability is implementation dependent feature in armv7
+ * specification, for now safe value (disable outer shareability is used)
+ * NOS[0:7] = 1
*/
-#if ARM_ARCH_6 || ARM_ARCH_7A
-#ifdef SMP
-#define PTE_NOCACHE 2
-#else
-#define PTE_NOCACHE 1
-#endif
-#define PTE_CACHE 4
-#define PTE_DEVICE 2
-#define PTE_PAGETABLE 4
+
+#define PRRR 0xff0a8aa4
+#define NMRR 0xc7804780
+
+/*
+ * ARM_V6 and ARM_V7 TTBR bit definition
+ */
+#if defined(ARM_MMU_V6) || defined (ARM_MMU_V7)
+#define PT_NOS (1 << 5)
+#define PT_S (1 << 1)
+#define PT_OUTER_NC 0
+#define PT_OUTER_WT (2 << 3)
+#define PT_OUTER_WB (3 << 3)
+#define PT_OUTER_WBWA (1 << 3)
+#if defined(SMP)
+#define PT_SHAREABLE (PT_S)
+#define PT_INNER_NC 0
+#define PT_INNER_WT (1 << 0)
+#define PT_INNER_WB ((1 << 0) | (1 << 6))
+#define PT_INNER_WBWA (1 << 6)
#else
+#define PT_SHAREABLE 0
+
+/*
+ * In ARMv6 and ARMV7 without multiprocessor extension,
+ * pagetable memory inner cacheability policy is implementation defined
+ */
+#define PT_INNER_NC 0
+#define PT_INNER_WT (1 << 0)
+#define PT_INNER_WB (1 << 0)
+#define PT_INNER_WBWA (1 << 0)
+#endif /* SMP */
+
+#define TTB_FLAGS_0 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC)
+#define TTB_FLAGS_1 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC)
+#define TTB_FLAGS_2 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC)
+#define TTB_FLAGS_3 (PT_SHAREABLE | PT_NOS | PT_INNER_WT | PT_OUTER_WT)
+#define TTB_FLAGS_4 (PT_SHAREABLE | PT_NOS | PT_INNER_WB | PT_OUTER_WB)
+#define TTB_FLAGS_5 (PT_SHAREABLE | PT_NOS | PT_INNER_WBWA | PT_OUTER_WBWA)
+#define TTB_FLAGS_6 (PT_SHAREABLE | PT_NOS | PT_INNER_NC | PT_OUTER_NC)
+#define TTB_FLAGS_7 (PT_SHAREABLE | PT_NOS | PT_INNER_WBWA | PT_OUTER_WB)
+#endif /* ARM_MMU_V6 || ARM_MMU_V7 */
+
+/*
+ * Pte related macros
+ *
+ * Memory types when tex remap is enabled (armv6 and armv7):
+ * 0 - strongly ordered
+ * 1 - device memory,
+ * 2 - normal memory, non cacheable
+ * 3 - normal memory, inner write-through, outer write-through
+ * 4 - normal memory, inner write-back, outer write-back
+ * 5 - normal memory, inner write-back write-allocate,
+ * outer write-back write-allocate
+ * 6 - reserved value
+ * 7 - normal memory, inner write-back write-allocate, outer write-back
+ *
+ * Memory types when tex remap is disabled / not supported:
+ * 0 - strongly ordered
+ * 1 - device memory, non shareable
+ * 2 - device memory, shareable
+ * 3 - normal memory, non cacheable
+ * 4 - normal memory, inner write-through, outer write-through
+ * 5 - normal memory, inner write-back, outer write-back
+ * 6 - normal memory, inner write-back write-allocate,
+ * outer write-back write-allocate
+ */
+
+#if defined(ARM_MMU_V6) || defined (ARM_MMU_V7)
+#define PTE_NOCACHE 2
+#define PTE_CACHE 3
+#define PTE_DEVICE 1
+
+/* TTB_FLAGS number must be the same as PTE_PAGETABLE value */
+#define PTE_PAGETABLE 3
+#define TTB_ATTR TTB_FLAGS_3
+#else /* ARM_MMU_V6 || ARM_MMU_V7 */
#define PTE_NOCACHE 1
#define PTE_CACHE 2
#define PTE_PAGETABLE 3
-#endif
+#endif /* ARM_MMU_V6 || ARM_MMU_V7 */
-enum mem_type {
- STRONG_ORD = 0,
- DEVICE_NOSHARE,
- DEVICE_SHARE,
- NRML_NOCACHE,
- NRML_IWT_OWT,
- NRML_IWB_OWB,
- NRML_IWBA_OWBA
-};
#ifndef LOCORE
@@ -370,55 +464,6 @@ extern int pmap_needs_pte_sync;
#define L1_C_PROTO (L1_TYPE_C)
#define L2_S_PROTO (L2_TYPE_S)
-#ifndef SMP
-#define ARM_L1S_STRONG_ORD (0)
-#define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2))
-#define ARM_L1S_DEVICE_SHARE (L1_S_B)
-#define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1))
-#define ARM_L1S_NRML_IWT_OWT (L1_S_C)
-#define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B)
-#define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B)
-
-#define ARM_L2L_STRONG_ORD (0)
-#define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2))
-#define ARM_L2L_DEVICE_SHARE (L2_B)
-#define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1))
-#define ARM_L2L_NRML_IWT_OWT (L2_C)
-#define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B)
-#define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B)
-
-#define ARM_L2S_STRONG_ORD (0)
-#define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2))
-#define ARM_L2S_DEVICE_SHARE (L2_B)
-#define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1))
-#define ARM_L2S_NRML_IWT_OWT (L2_C)
-#define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B)
-#define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B)
-#else
-#define ARM_L1S_STRONG_ORD (0)
-#define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2))
-#define ARM_L1S_DEVICE_SHARE (L1_S_B)
-#define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)|L1_SHARED)
-#define ARM_L1S_NRML_IWT_OWT (L1_S_C|L1_SHARED)
-#define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B|L1_SHARED)
-#define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED)
-
-#define ARM_L2L_STRONG_ORD (0)
-#define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2))
-#define ARM_L2L_DEVICE_SHARE (L2_B)
-#define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)|L2_SHARED)
-#define ARM_L2L_NRML_IWT_OWT (L2_C|L2_SHARED)
-#define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
-#define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED)
-
-#define ARM_L2S_STRONG_ORD (0)
-#define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2))
-#define ARM_L2S_DEVICE_SHARE (L2_B)
-#define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)|L2_SHARED)
-#define ARM_L2S_NRML_IWT_OWT (L2_C|L2_SHARED)
-#define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED)
-#define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED)
-#endif /* SMP */
#endif /* ARM_NMMUS > 1 */
#if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1)
@@ -427,6 +472,12 @@ extern int pmap_needs_pte_sync;
#elif defined(CPU_XSCALE_81342)
#define PMAP_NEEDS_PTE_SYNC 1
#define PMAP_INCLUDE_PTE_SYNC
+#elif defined(ARM_ARCH_6) || defined(ARM_ARCH_7A)
+#if PTE_PAGETABLE > 2
+#define PMAP_NEEDS_PTE_SYNC 1
+#else
+#define PMAP_NEEDS_PTE_SYNC 0
+#endif /* PTE_PAGETABLE > 2 */
#elif (ARM_MMU_SA1 == 0)
#define PMAP_NEEDS_PTE_SYNC 0
#endif
-------------- next part --------------
commit c9d6668535dd4a18a1a773b37f02f84482f9db84
Author: Lukasz Plachno <luk at semihalf.com>
Date: Mon Nov 19 10:14:41 2012 +0100
arm/smp: Various fixes for enabling SMP operation on ARM systems
- Currently libc is built with ARM SMP support only if specified architecture is one
of the following:
- armv6k
- armv6zk
- armv7
- armv7a
- None of currently available CPUTYPE options allows us to choose one of architectures
above, thus additional target is needed. From now on world for multicore ARM targets
should be built with -CPUTYPE=armv6k or -CPUTYPE=cortexa
- Completely remove option ARM_TP_ADDRESS (no longer used)
- Propagate TLB maintenance operations in SMP mode (follow up for changes proposed
by Giovanni Trematerra)
- pcpup pointer is common for every core, thus using it is not SMP safe
diff --git a/share/mk/bsd.cpu.mk b/share/mk/bsd.cpu.mk
index 4f9527c..47c47c7 100644
--- a/share/mk/bsd.cpu.mk
+++ b/share/mk/bsd.cpu.mk
@@ -97,13 +97,15 @@ _CPUCFLAGS = -march=${CPUTYPE}
. if ${CPUTYPE} == "xscale"
#XXX: gcc doesn't seem to like -mcpu=xscale, and dies while rebuilding itself
#_CPUCFLAGS = -mcpu=xscale
-_CPUCFLAGS = -march=armv5te -D__XSCALE__ -DARM_WANT_TP_ADDRESS
+_CPUCFLAGS = -march=armv5te -D__XSCALE__
. elif ${CPUTYPE} == "armv6"
_CPUCFLAGS = -march=${CPUTYPE} -DARM_ARCH_6=1
+. elif ${CPUTYPE} == "armv6k"
+_CPUCFLAGS = -march=${CPUTYPE} -DARM_ARCH_6=1
. elif ${CPUTYPE} == "cortexa"
-_CPUCFLAGS = -march=armv6 -DARM_ARCH_6=1 -mfpu=vfp
+_CPUCFLAGS = -march=armv6k -DARM_ARCH_6=1 -mfpu=vfp
. else
-_CPUCFLAGS = -mcpu=${CPUTYPE} -DARM_WANT_TP_ADDRESS
+_CPUCFLAGS = -mcpu=${CPUTYPE}
. endif
. elif ${MACHINE_ARCH} == "powerpc"
. if ${CPUTYPE} == "e500"
diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S
index e81912c..99b214a 100644
--- a/sys/arm/arm/locore.S
+++ b/sys/arm/arm/locore.S
@@ -166,7 +166,11 @@ Lunmapped:
orr r0, r0, #2 /* Set TTB shared memory flag */
#endif
mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
- mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
+#ifdef SMP
+ mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */
+#else
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
+#endif
#if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
mov r0, #0
@@ -361,7 +365,11 @@ Ltag:
orr r0, r0, #0 /* Set TTB shared memory flag */
#endif
mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
- mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
+#ifdef SMP
+ mcr p15, 0, r0, c8, c3, 0 /* Invalidate I+D TLBs Inner Shareable */
+#else
+ mcr p15, 0, r0, c8, c7, 0 /* Invalidate I+D TLBs */
+#endif
#if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA)
mov r0, #0
diff --git a/sys/arm/include/pcpu.h b/sys/arm/include/pcpu.h
index f12f903..43ffb44 100644
--- a/sys/arm/include/pcpu.h
+++ b/sys/arm/include/pcpu.h
@@ -100,8 +100,8 @@ set_tls(void *tls)
#define PCPU_GET(member) (get_pcpu()->pc_ ## member)
#define PCPU_ADD(member, value) (get_pcpu()->pc_ ## member += (value))
#define PCPU_INC(member) PCPU_ADD(member, 1)
-#define PCPU_PTR(member) (&pcpup->pc_ ## member)
-#define PCPU_SET(member,value) (pcpup->pc_ ## member = (value))
+#define PCPU_PTR(member) (&get_pcpu()->pc_ ## member)
+#define PCPU_SET(member,value) (get_pcpu()->pc_ ## member = (value))
void pcpu0_init(void);
#endif /* _KERNEL */
diff --git a/sys/conf/options.arm b/sys/conf/options.arm
index 2fe7b9f..e9c8187 100644
--- a/sys/conf/options.arm
+++ b/sys/conf/options.arm
@@ -7,7 +7,6 @@ ARM_L2_PIPT opt_global.h
ARM_MANY_BOARD opt_global.h
ARM_USE_SMALL_ALLOC opt_global.h
ARM_VFP_SUPPORT opt_global.h
-ARM_WANT_TP_ADDRESS opt_global.h
COUNTS_PER_SEC opt_timer.h
CPU_ARM9 opt_global.h
CPU_ARM9E opt_global.h
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