Cache in write-back problem for armv6

[Grzegorz Bernacki]

Hi,

I've investigated problem which we have on our target when we switch 
cache to write-back mode. I've find out that the page tables were 
corrupted by some data. Those data turned out to be slab pointers. So my 
theory is that after slab has been allocated for page table we still 
have some dirty cache lines for this slab (at the begining of the slab 
we keep list pointers, which are updated on allocation/free) and we need 
to write-back/invalidate it before we downgrade this page to WT mode. 
Please see patch below and let me know if it helps you (it works for me, 
but maybe as a side effect)

regards,
grzesiek

diff --git a/sys/arm/arm/pmap-v6.c b/sys/arm/arm/pmap-v6.c
index 0aa0f10..9518658 100644
--- a/sys/arm/arm/pmap-v6.c
+++ b/sys/arm/arm/pmap-v6.c
@@ -809,6 +809,12 @@ pmap_l2ptp_ctor(void *mem, int size, void *arg, int 
flags)
         ptep = &l2b->l2b_kva[l2pte_index(va)];
         pte = *ptep;

+       cpu_idcache_wbinv_range(va, PAGE_SIZE);
+#ifdef ARM_L2_PIPT
+       cpu_l2cache_wbinv_range(pte & L2_S_FRAME, PAGE_SIZE);
+#else
+       cpu_l2cache_wbinv_range(va, PAGE_SIZE);
+#endif
         if ((pte & L2_S_CACHE_MASK) != pte_l2_s_cache_mode_pt) {
                 /*
                  * Page tables must have the cache-mode set to