svn commit: r186730 - in head: lib/libusb20 sys/dev/usb2/controller sys/dev/usb2/core sys/dev/usb2/ethernet sys/dev/usb2/image sys/dev/usb2/include sys/dev/usb2/serial sys/dev/usb2/sound sys/dev/us...

[Stanislav Sedov]

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On Wed, 7 Jan 2009 12:46:14 -0600 (CST)
Mark Tinguely <tinguely at casselton.net> mentioned:

> It could be the same problem if there is a duplicate kernel mapping. If
> there is no duplicate kernel mapping, then there is another cache leak
> somewhere.
> 

Yeah, it seems it leaks somewhere as invalidating the entire wb cache
in case of coherent mapping in sys/arm/arm/busdma_machdep.c:_bus_dmamap_sync,
where currently it simply returns solves the problem. In fact, all usb memory
is mapped as coherent and thus should not require cache flush, but something
goes wrong. Could additional entries established by arm_remap_nocache in
case of coherent mapping interfere with previous mappings and thus create
problems? Is it the same case as duplicate mappings?

Thanks!
- -- 
Stanislav Sedov
ST4096-RIPE
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