superpages for UMA

[Warner Losh]

On Aug 18, 2014, at 2:13 PM, Peter Grehan <grehan at freebsd.org> wrote:

>> Newer Intel CPUs have more entries, and AMD CPUs have long (since
>> Barcelona) had more.  In particular, they allow 2 MB page mappings to be
>> cached in a larger L2 TLB.  Nowadays, the trouble is with the 1 GB pages.
>> A lot of CPUs still only support an 8 entry, 1 level TLB for 1 GB pages.
> 
> There are new(ish) ones effectively without 1GB pages. From the "Software Optimization Guide for AMD Family 16h Processors"
> 
> "Smashing"
>  ...
> "when the Family 16h processor encounters a 1-Gbyte page size, it will smash translations of that 1-Gbyte region into 2-Mbyte TLB entries, each
> of which translates a 2-Mbyte region of the 1-Gbyte page."

“we’ll emulate this feature designed to make things go faster in hardware in software by doing the very thing that makes it go slow in hardware.”

Fun times. Performance Smashing!

Warner

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