[patch] Adding optimized kernel copying support - Part III

[Alexander Leidinger]

Quoting Attilio Rao <asmrookie at gmail.com> (from Thu, 1 Jun 2006  
01:32:12 +0200):

> 2006/6/1, Bruce Evans <bde at zeta.org.au>:

>> The new code wouldn't behave much differently under SMP.  It just might
>> be a smaller optimization because more memory pressure for SMP causes
>> more cache misses for everything and there are no benefits from copying
>> through MMX/XMM unless nontemporal writes are used.  All (?) CPUs with
>> MMX or SSE* can saturate main memory using 32-bit instructions.  On
>> 32-bit CPUs, the benefits of using MMX/XMM come from being able to
>> saturate the L1 cache on some CPUs (mainly Athlons and not P[2-4]),
>> and from being able to use nontemporal writes on some CPUs (at least
>> AthlonXP via SSE extensions all CPUs with SSE2).
>
> I was just speaking about the copying routine itself and not about the
> SSE2 environment preserving mechanism. It remains untouched in SMP
> case.

AFAIR the DFly FPU rework allows to use FPU/XMM instructions in their  
kernel without the need to do some manual state preserving (it's done  
automatically on demand). So one could use XMM instructions in RAID 5  
or crypto parts of the code to test if it is a performance benefit. Do  
I understand the above part right that with this patch this is also  
the case for us in the UP case, but not in the SMP case?

Bye,
Alexander.

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