The relation between %fs and fs base

[jj shen]

Hi,

I want to access different TLS through both fs base and GDT simultaneously.
Let us call the two ways TLS_FSBASE and TLS_GDT respectively.

(1) Can I switch from TLS_FSBASE to TLS_GDT just by: "movl GDT_SEL, %fs"
(where GDT_SEL is the selector of GDT entry)?
Will this instruction destroy the content of the IA32_FS_BASE MSR?

(2) When switching from TLS_GDT to TLS_FSBASE, can I just set %fs to zero to
indicate the fs base should be used, or must I invoke the
*wrmsrl*instruction to reset IA32_FS_BASE once again?

(3) What is the length of %fs? What I get by "movl %fs, %eax" in %eax?
    In the programmer manual from AMD, it is said somewhere that segment
registers are still 16 bits as in x86, and it is also said otherwhere that
"segment loads into FS and GS load a standard 32-bit base value in the
hidden portion of the segment descriptor register".

 (4) What is the content of %fs, a descriptor selector or a base address
smaller than 0xffffffff?
What is effect of "movl val, %fs", loading a GDT selector or a 32-bit base
address to %fs?
    Seen from the citation above, I think *val *should be a 32-bit base
address; however seen from the implementation of Linux *arch_prctl* system
call, it is a GDT selector loaded into %fs.

Anyone help me?

Thanks,

Dimension