git: 8f1562430fbb - main - Add Apollo Lake SIO/LPSS UARTs PCI IDs

[Konstantin Belousov]

The branch main has been updated by kib:

URL: https://cgit.FreeBSD.org/src/commit/?id=8f1562430fbb83f6cedff6450e1aa1b593e3d7e7

commit 8f1562430fbb83f6cedff6450e1aa1b593e3d7e7
Author:     Jose Luis Duran <jlduran at gmail.com>
AuthorDate: 2021-05-02 21:20:25 +0000
Commit:     Konstantin Belousov <kib at FreeBSD.org>
CommitDate: 2021-05-03 11:38:52 +0000

    Add Apollo Lake SIO/LPSS UARTs PCI IDs
    
    Add PCI IDs for Intel Apollo Lake Series HSUARTs:
    
        # pciconf -ll
        drv   selector      class    rev  hdr  vendor device subven subdev
        uart0 at pci0:0:24:0:  118000   0b   00   8086   5abc   8086   7270
        uart1 at pci0:0:24:1:  118000   0b   00   8086   5abe   8086   7270
        uart2 at pci0:0:24:2:  118000   0b   00   8086   5ac0   8086   7270
        uart3 at pci0:0:24:3:  118000   0b   00   8086   5aee   8086   7270
    
    NB (Intel Document Number 336256-004US):
    1. The E3900 and A3900 Series Processors support four LPSS_UART ports,
       while the N- and J- Series Processors support only LPSS_UART [2:1]
       ports.
    2. The LPSS_UART1 port is dedicated for discrete Global Navigation
       Satellite System (GNSS).  This port can be used for generic UART
       functionality if GNSS is not used.
    3. The LPSS_UART2 port is dedicated for host OS debug.
    4. The LPSS_UART0 and LPSS_UART3 ports are for generic UART functionality.
    5. Only UART [1:0] ports support DMA.
    
    PR:     255556
    Submitted by:   Jose Luis Duran <jlduran at gmail.com>
    MFC after:      1 week
---
 sys/dev/uart/uart_bus_pci.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/sys/dev/uart/uart_bus_pci.c b/sys/dev/uart/uart_bus_pci.c
index 123ee3e26829..707b82dc078b 100644
--- a/sys/dev/uart/uart_bus_pci.c
+++ b/sys/dev/uart/uart_bus_pci.c
@@ -147,6 +147,14 @@ static const struct pci_id pci_ns8250_ids[] = {
 { 0x8086, 0x2e17, 0xffff, 0, "4 Series Chipset Serial KT Controller", 0x10 },
 { 0x8086, 0x3b67, 0xffff, 0, "5 Series/3400 Series Chipset KT Controller",
 	0x10 },
+{ 0x8086, 0x5abc, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 0", 0x10,
+	24 * DEFAULT_RCLK, 2 },
+{ 0x8086, 0x5abe, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 1", 0x10,
+	24 * DEFAULT_RCLK, 2 },
+{ 0x8086, 0x5ac0, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 2", 0x10,
+	24 * DEFAULT_RCLK, 2 },
+{ 0x8086, 0x5aee, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 3", 0x10,
+	24 * DEFAULT_RCLK, 2 },
 { 0x8086, 0x8811, 0xffff, 0, "Intel EG20T Serial Port 0", 0x10 },
 { 0x8086, 0x8812, 0xffff, 0, "Intel EG20T Serial Port 1", 0x10 },
 { 0x8086, 0x8813, 0xffff, 0, "Intel EG20T Serial Port 2", 0x10 },