git: 6c9b3cb4936e - stable/13 - spigen.4: Fix typos

[Mateusz Piotrowski]

The branch stable/13 has been updated by 0mp (doc, ports committer):

URL: https://cgit.FreeBSD.org/src/commit/?id=6c9b3cb4936e789ca43338a5f92a36fa51b2f7c2

commit 6c9b3cb4936e789ca43338a5f92a36fa51b2f7c2
Author:     Mateusz Piotrowski <0mp at FreeBSD.org>
AuthorDate: 2021-04-18 07:45:18 +0000
Commit:     Mateusz Piotrowski <0mp at FreeBSD.org>
CommitDate: 2021-04-21 07:50:58 +0000

    spigen.4: Fix typos
    
    MFC after:      3 days
    
    (cherry picked from commit 40277af7f23405c276edf02c3ddc8e770a06e3f6)
---
 share/man/man4/spigen.4 | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/share/man/man4/spigen.4 b/share/man/man4/spigen.4
index e586b0baa82a..8a8cc556be81 100644
--- a/share/man/man4/spigen.4
+++ b/share/man/man4/spigen.4
@@ -57,7 +57,7 @@ device is associated with a single chip-select
 line on the bus, and all I/O performed through that instance is done
 with that chip-select line asserted.
 .Pp
-SPI data transfers are inherently bi-directional; there are not separate
+SPI data transfers are inherently bi-directional; there are no separate
 read and write operations.
 When commands and data are sent to a device, data also comes back from
 the device, although in some cases the data may not be useful (or even
@@ -117,7 +117,7 @@ Set the maximum clock speed (bus frequency in Hertz) to be used
 when communicating with this slave device.
 The setting remains in effect for subsequent transfers; it
 is not necessary to reset this before each transfer.
-The actual bus frequency may be lower due to hardware limitiations
+The actual bus frequency may be lower due to hardware limitations
 of the SPI bus controller device.
 .It Dv SPIGENIOC_GET_SPI_MODE Pq Vt uint32_t
 Get the SPI mode (clock polarity and phase) to be used