git: a7a80f17715c - stable/13 - mlx5: Add new timestamp mode bits.
Hans Petter Selasky
hselasky at FreeBSD.org
Mon Jul 26 16:13:49 UTC 2021
The branch stable/13 has been updated by hselasky:
URL: https://cgit.FreeBSD.org/src/commit/?id=a7a80f17715c7b71c9de66f127fb4b3e6b4b267a
commit a7a80f17715c7b71c9de66f127fb4b3e6b4b267a
Author: Hans Petter Selasky <hselasky at FreeBSD.org>
AuthorDate: 2021-06-16 13:01:52 +0000
Commit: Hans Petter Selasky <hselasky at FreeBSD.org>
CommitDate: 2021-07-26 16:04:32 +0000
mlx5: Add new timestamp mode bits.
These fields declare which timestamp mode is supported
by the device per RQ/SQ/QP.
In addition add the ts_format field to the select the mode
for RQ/SQ/QP.
Linux commit:
a6a217dddcd544f6b75f0e2a60b6e84c1d494b7e
Reviewed by: kib
Sponsored by: Mellanox Technologies // NVIDIA Networking
(cherry picked from commit 915fc66cb59faa543b852083233729c270d5aa3b)
---
sys/dev/mlx5/mlx5_ifc.h | 56 +++++++++++++++++++++++++++++++++++++++++++------
1 file changed, 50 insertions(+), 6 deletions(-)
diff --git a/sys/dev/mlx5/mlx5_ifc.h b/sys/dev/mlx5/mlx5_ifc.h
index 494180630500..ce8074fba3f1 100644
--- a/sys/dev/mlx5/mlx5_ifc.h
+++ b/sys/dev/mlx5/mlx5_ifc.h
@@ -914,13 +914,19 @@ enum {
MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4,
};
+enum {
+ MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
+ MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
+ MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
+};
+
struct mlx5_ifc_roce_cap_bits {
u8 roce_apm[0x1];
u8 rts2rts_primary_eth_prio[0x1];
u8 roce_rx_allow_untagged[0x1];
u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
-
- u8 reserved_0[0x1c];
+ u8 reserved_at_4[0x1a];
+ u8 qp_ts_format[0x2];
u8 reserved_1[0x60];
@@ -1037,6 +1043,18 @@ enum {
MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
};
+enum {
+ MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
+ MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
+ MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
+};
+
+enum {
+ MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
+ MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
+ MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
+};
+
struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_0[0x80];
@@ -1274,7 +1292,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 general_obj_types[0x40];
- u8 reserved_at_440[0x8];
+ u8 sq_ts_format[0x2];
+ u8 rq_ts_format[0x2];
+ u8 reserved_at_444[0x4];
u8 create_qp_start_hint[0x18];
u8 reserved_at_460[0x3];
@@ -1961,6 +1981,12 @@ enum {
MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
};
+enum {
+ MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
+ MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
+ MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
+};
+
struct mlx5_ifc_qpc_bits {
u8 state[0x4];
u8 lag_tx_port_affinity[0x4];
@@ -1987,7 +2013,9 @@ struct mlx5_ifc_qpc_bits {
u8 log_rq_stride[0x3];
u8 no_sq[0x1];
u8 log_sq_size[0x4];
- u8 reserved_7[0x6];
+ u8 reserved_at_55[0x3];
+ u8 ts_format[0x2];
+ u8 reserved_at_5a[0x1];
u8 rlky[0x1];
u8 ulp_stateless_offload_mode[0x4];
@@ -2376,6 +2404,12 @@ enum {
MLX5_SQC_STATE_ERR = 0x3,
};
+enum {
+ MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
+ MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
+ MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
+};
+
struct mlx5_ifc_sqc_bits {
u8 rlkey[0x1];
u8 cd_master[0x1];
@@ -2386,7 +2420,9 @@ struct mlx5_ifc_sqc_bits {
u8 state[0x4];
u8 reg_umr[0x1];
u8 allow_swp[0x1];
- u8 reserved_0[0x12];
+ u8 reserved_at_e[0xc];
+ u8 ts_format[0x2];
+ u8 reserved_at_1c[0x4];
u8 reserved_1[0x8];
u8 user_index[0x18];
@@ -2492,6 +2528,12 @@ enum {
MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1,
};
+enum {
+ MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
+ MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
+ MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
+};
+
struct mlx5_ifc_rqc_bits {
u8 rlkey[0x1];
u8 delay_drop_en[0x1];
@@ -2501,7 +2543,9 @@ struct mlx5_ifc_rqc_bits {
u8 state[0x4];
u8 reserved_1[0x1];
u8 flush_in_error_en[0x1];
- u8 reserved_2[0x12];
+ u8 reserved_at_e[0xc];
+ u8 ts_format[0x2];
+ u8 reserved_at_1c[0x4];
u8 reserved_3[0x8];
u8 user_index[0x18];
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