git: 04d2d2d7fd22 - main - cgem: improve usage of busdma(9) KPI

[Mitchell Horne]

On Thu, Feb 18, 2021 at 5:19 PM Mitchell Horne <mhorne at freebsd.org> wrote:
>
> The branch main has been updated by mhorne:
>
> URL: https://cgit.FreeBSD.org/src/commit/?id=04d2d2d7fd22bba638ccb5a0b2e0805087a70cd3
>
> commit 04d2d2d7fd22bba638ccb5a0b2e0805087a70cd3
> Author:     Mitchell Horne <mhorne at FreeBSD.org>
> AuthorDate: 2021-01-20 15:07:53 +0000
> Commit:     Mitchell Horne <mhorne at FreeBSD.org>
> CommitDate: 2021-02-18 21:17:41 +0000
>
>     cgem: improve usage of busdma(9) KPI
>
>     BUS_DMA_NOCACHE should only be used when one needs to guarantee the
>     created mapping has uncached memory attributes, usually as a result
>     of buggy hardware. Normal use cases should pass BUS_DMA_COHERENT, to
>     create an appropriate mapping based on the flags passed to
>     bus_dma_tag_create().
>
>     This should have no functional change, since the DMA tags in this driver
>     are created without the BUS_DMA_COHERENT flag.
>
>     Reported by:    mmel
>     Reviewed by:    mmel, Thomas Skibo <thomas-bsd at skibo.net>
>     MFC after:      3 days

Whoops, forgot to include:

Differential Revision: https://reviews.freebsd.org/D28775

> ---
>  sys/dev/cadence/if_cgem.c | 12 ++++--------
>  1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/sys/dev/cadence/if_cgem.c b/sys/dev/cadence/if_cgem.c
> index 81fc39b831af..0583e846458a 100644
> --- a/sys/dev/cadence/if_cgem.c
> +++ b/sys/dev/cadence/if_cgem.c
> @@ -443,17 +443,13 @@ cgem_setup_descs(struct cgem_softc *sc)
>                 return (err);
>
>         /*
> -        * Allocate DMA memory in non-cacheable space.  We allocate transmit,
> -        * receive and null descriptor queues all at once because the
> -        * hardware only provides one register for the upper 32 bits of
> -        * rx and tx descriptor queues hardware addresses.
> +        * Allocate DMA memory. We allocate transmit, receive and null
> +        * descriptor queues all at once because the hardware only provides
> +        * one register for the upper 32 bits of rx and tx descriptor queues
> +        * hardware addresses.
>          */
>         err = bus_dmamem_alloc(sc->desc_dma_tag, (void **)&sc->rxring,
> -#ifdef __arm__
>             BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO,
> -#else
> -           BUS_DMA_NOWAIT | BUS_DMA_NOCACHE | BUS_DMA_ZERO,
> -#endif
>             &sc->rxring_dma_map);
>         if (err)
>                 return (err);