git: f41cab0fade0 - main - cad/verilator: Backport the fix of bug that caused wrong C++ code generation

[Yuri Victorovich]

The branch main has been updated by yuri:

URL: https://cgit.FreeBSD.org/ports/commit/?id=f41cab0fade0722df7e0b5c34ace200967399ea7

commit f41cab0fade0722df7e0b5c34ace200967399ea7
Author:     Yuri Victorovich <yuri at FreeBSD.org>
AuthorDate: 2021-08-25 20:24:58 +0000
Commit:     Yuri Victorovich <yuri at FreeBSD.org>
CommitDate: 2021-08-25 20:28:24 +0000

    cad/verilator: Backport the fix of bug that caused wrong C++ code generation
---
 cad/verilator/Makefile | 4 ++++
 cad/verilator/distinfo | 4 +++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/cad/verilator/Makefile b/cad/verilator/Makefile
index 7cecedcda41b..5f7e8d0323f2 100644
--- a/cad/verilator/Makefile
+++ b/cad/verilator/Makefile
@@ -1,8 +1,12 @@
 PORTNAME=	verilator
 DISTVERSION=	4.210
+PORTREVISION=	1
 CATEGORIES=	cad
 MASTER_SITES=	https://www.veripool.org/ftp/
 
+PATCH_SITES=	https://github.com/verilator/verilator/commit/
+PATCHFILES=	9907d211ff5fa408a7eb6387ef0ceaedaeea2d32.patch:-p1 # backport of bug fix: https://github.com/verilator/verilator/commit/9907d211ff5fa408a7eb6387ef0ceaedaeea2d32
+
 MAINTAINER=	yuri at FreeBSD.org
 COMMENT=	Synthesizable Verilog to C++ compiler
 
diff --git a/cad/verilator/distinfo b/cad/verilator/distinfo
index cb22cc780c7a..3f71f9bc0120 100644
--- a/cad/verilator/distinfo
+++ b/cad/verilator/distinfo
@@ -1,3 +1,5 @@
-TIMESTAMP = 1627977232
+TIMESTAMP = 1629920311
 SHA256 (verilator-4.210.tgz) = 2a821f25e5766884e7c22076790810a386725df31ee9eac58862977b347e2018
 SIZE (verilator-4.210.tgz) = 3229756
+SHA256 (9907d211ff5fa408a7eb6387ef0ceaedaeea2d32.patch) = 52418f475136134e139e70fcdacaedd9f2baa1cd17daa5c0d7e72054dcf87024
+SIZE (9907d211ff5fa408a7eb6387ef0ceaedaeea2d32.patch) = 2303