cvs commit: src/sys/boot/sparc64/loader main.c src/sys/sparc64/sparc64 exception.S mp_exception.S pmap.c support.S swtch.S tlb.c

[Marius Strobl]

marius      2008-09-08 20:38:48 UTC

  FreeBSD src repository

  Modified files:
    sys/boot/sparc64/loader main.c 
    sys/sparc64/sparc64  exception.S mp_exception.S pmap.c 
                         support.S swtch.S tlb.c 
  Log:
  SVN rev 182877 on 2008-09-08 20:38:48Z by marius
  
  USIII and beyond CPUs have stricter requirements when it comes
  to synchronization needed after stores to internal ASIs in order
  to make side-effects visible. This mainly requires the MEMBAR #Sync
  after such stores to be replaced with a FLUSH. We use KERNBASE as
  the address to FLUSH as it is guaranteed to not trap. Actually,
  the USII synchronization rules also already require a FLUSH in
  pretty much all of the cases changed.
  We're also hitting an additional USIII synchronization rule which
  requires stores to AA_IMMU_SFSR to be immediately followed by a DONE,
  FLUSH or RETRY. Doing so triggers a RED state exception though so
  leave the MEMBAR #Sync. Linux apparently also has gotten away with
  doing the same for quite some time now, apart from the fact that
  it's not clear to me why we need to clear the valid bit from the
  SFSR in the first place.
  
  Reviewed by:    nwhitehorn
  
  Revision  Changes    Path
  1.37      +2 -1      src/sys/boot/sparc64/loader/main.c
  1.80      +12 -1     src/sys/sparc64/sparc64/exception.S
  1.15      +7 -5      src/sys/sparc64/sparc64/mp_exception.S
  1.176     +2 -2      src/sys/sparc64/sparc64/pmap.c
  1.34      +2 -1      src/sys/sparc64/sparc64/support.S
  1.36      +2 -1      src/sys/sparc64/sparc64/swtch.S
  1.11      +4 -3      src/sys/sparc64/sparc64/tlb.c