cvs commit: src/sys/i386/i386 pmap.c src/sys/i386/include pmap.h

[Alan Cox]

alc         2008-03-27 04:34:18 UTC

  FreeBSD src repository

  Modified files:
    sys/i386/i386        pmap.c 
    sys/i386/include     pmap.h 
  Log:
  MFamd64 with few changes:
  
  1. Add support for automatic promotion of 4KB page mappings to 2MB page
     mappings.  Automatic promotion can be enabled by setting the tunable
     "vm.pmap.pg_ps_enabled" to a non-zero value.  By default, automatic
     promotion is disabled.  Tested by: kris
  
  2. To date, we have assumed that the TLB will only set the PG_M bit in a
     PTE if that PTE has the PG_RW bit set.  However, this assumption does
     not hold on recent processors from Intel.  For example, consider a PTE
     that has the PG_RW bit set but the PG_M bit clear.  Suppose this PTE
     is cached in the TLB and later the PG_RW bit is cleared in the PTE,
     but the corresponding TLB entry is not (yet) invalidated.
     Historically, upon a write access using this (stale) TLB entry, the
     TLB would observe that the PG_RW bit had been cleared and initiate a
     page fault, aborting the setting of the PG_M bit in the PTE.  Now,
     however, P4- and Core2-family processors will set the PG_M bit before
     observing that the PG_RW bit is clear and initiating a page fault.  In
     other words, the write does not occur but the PG_M bit is still set.
  
     The real impact of this difference is not that great.  Specifically,
     we should no longer assert that any PTE with the PG_M bit set must
     also have the PG_RW bit set, and we should ignore the state of the
     PG_M bit unless the PG_RW bit is set.
  
  Revision  Changes    Path
  1.610     +1094 -91  src/sys/i386/i386/pmap.c
  1.132     +16 -2     src/sys/i386/include/pmap.h