cvs commit: src/sys/i386/isa clock.c src/sys/amd64/isa clock.c

[Bruce Evans]

bde         2006-12-03 03:49:28 UTC

  FreeBSD src repository

  Modified files:
    sys/i386/isa         clock.c 
    sys/amd64/isa        clock.c 
  Log:
  Optimized RTC accesses by avoiding null writes to the index register
  and by only delaying when an RTC register is written to.  The delay
  after writing to the data register is now not just a workaround.
  
  This reduces the number of ISA accesses in the usual case from 4 to
  1.  The usual case is 2 rtcin()'s for each RTC interrupt.  The index
  register is almost always RTC_INTR for this.  The 3 extra ISA accesses
  were 1 for writing the index and 2 for delays.  Some delays are needed
  in theory, but in practice they now just slow down slow accesses some
  more since almost eveyone including us does them wrong so modern systems
  enforce sufficient delays in hardware.  I used to have the delays ifdefed
  out, but with the index register optimization the delays are rarely
  executed so the old magic ones can be kept or even implemented non-
  magically without significant cost.
  
  Optimizing RTC interrupt handling is more interesting than it used to
  be because RTC interrupts are currently needed to fix the more efficient
  apic timer interrupts on some systems.  apic_timer_hz is normally 2000
  so the RTC interrupt rate needs to be 2048 to keep the apic timer
  firing on such systems.  Without these changes, each RTC interrupt
  normally took 10 ISA accesses (2 PIC accesses and 2 sets of 4 RTC
  accesses).  Each ISA access takes 1-1.5uS so 10 of then at 2048 Hz
  takes 2-3% of a CPU.  Now 4 of them take 0.8-1.2% of a CPU.
  
  Revision  Changes    Path
  1.228     +16 -9     src/sys/amd64/isa/clock.c
  1.231     +16 -9     src/sys/i386/isa/clock.c