cvs commit: src/sys/alpha/alpha machdep.c src/sys/alpha/include cpuconf.h src/sys/alpha/pci lca.c lcareg.h

[Bernd Walter]

On Tue, Feb 01, 2005 at 06:49:33AM -0500, John Baldwin wrote:
> On Monday 31 January 2005 06:07 pm, Bernd Walter wrote:
> > ticso       2005-01-31 23:07:42 UTC
> >
> >   FreeBSD src repository
> >
> >   Modified files:
> >     sys/alpha/alpha      machdep.c
> >     sys/alpha/include    cpuconf.h
> >     sys/alpha/pci        lca.c lcareg.h
> >   Log:
> >   add cpu_idle support for 21066A based lca systems
> >
> >   Revision  Changes    Path
> >   1.229     +9 -1      src/sys/alpha/alpha/machdep.c
> >   1.14      +1 -0      src/sys/alpha/include/cpuconf.h
> >   1.21      +29 -0     src/sys/alpha/pci/lca.c
> >   1.4       +2 -0      src/sys/alpha/pci/lcareg.h
> 
> What exactly are the writes to this register doing btw?  Also, is there any 
> reason we shouldn't just be using the PAL call that waits for the next 
> interrupt instead?

It reduces clock speed until the next interrupt on 21066A CPUs
and is a nop on plain 21066 CPUs.

Would the PAL call work for SMP systems?

AFAIK no alpha CPU has native halt support so there is not much magic
that PAL can do for us.
What I've found out about this case is that alpha CPUs automaticaly
reduce power on unused parts and running just a tight loop, that works
without memory access, for a few microsecsonds might be more efficient
do do it ourself than calling PAL, which must be doing something
similar.
At least I think it is possible to reduce idle power consumption from
the current situation either way.

-- 
B.Walter                   BWCT                http://www.bwct.de
bernd at bwct.de                                  info at bwct.de